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sb/intel/bd82x6x: Use PCI bitwise ops

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Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.

Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.

Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Angel Pons 2020-06-07 22:09:01 +02:00 committed by Patrick Georgi
parent 7333ea91ea
commit c803f65206
14 changed files with 65 additions and 165 deletions
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54
src/southbridge/intel/bd82x6x/azalia.c
View file

@ -215,8 +215,6 @@ static void azalia_init(struct device *dev)
u8 *base; u8 *base;
struct resource *res; struct resource *res;
u32 codec_mask; u32 codec_mask;
u8 reg8;
u16 reg16;
u32 reg32; u32 reg32;
/* Find base address */ /* Find base address */
@ -236,48 +234,30 @@ static void azalia_init(struct device *dev)
reg32 |= RCBA32(CIR31) & 0xfe; reg32 |= RCBA32(CIR31) & 0xfe;
pci_write_config32(dev, 0x120, reg32); pci_write_config32(dev, 0x120, reg32);
reg16 = pci_read_config16(dev, 0x78); pci_or_config16(dev, 0x78, 1 << 11);
reg16 |= (1 << 11);
pci_write_config16(dev, 0x78, reg16);
} else } else
printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
reg32 = pci_read_config32(dev, 0x114); pci_and_config32(dev, 0x114, ~0xfe);
reg32 &= ~0xfe;
pci_write_config32(dev, 0x114, reg32);
// Set VCi enable bit // Set VCi enable bit
reg32 = pci_read_config32(dev, 0x120); pci_or_config32(dev, 0x120, 1 << 31);
reg32 |= (1 << 31);
pci_write_config32(dev, 0x120, reg32);
// Enable HDMI codec: // Enable HDMI codec:
reg32 = pci_read_config32(dev, 0xc4); pci_or_config32(dev, 0xc4, 1 << 1);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xc4, reg32);
reg8 = pci_read_config8(dev, 0x43); pci_or_config8(dev, 0x43, 1 << 6);
reg8 |= (1 << 6);
pci_write_config8(dev, 0x43, reg8);
/* Additional programming steps */ /* Additional programming steps */
reg32 = pci_read_config32(dev, 0xc4); pci_or_config32(dev, 0xc4, 1 << 13);
reg32 |= (1 << 13);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xc4); pci_or_config32(dev, 0xc4, 1 << 10);
reg32 |= (1 << 10);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xd0); pci_and_config32(dev, 0xd0, ~(1 << 31));
reg32 &= ~(1 << 31);
pci_write_config32(dev, 0xd0, reg32);
if (dev->device == 0x1e20) { if (dev->device == 0x1e20) {
/* Additional step on Panther Point */ /* Additional step on Panther Point */
reg32 = pci_read_config32(dev, 0xc4); pci_or_config32(dev, 0xc4, 1 << 17);
reg32 |= (1 << 17);
pci_write_config32(dev, 0xc4, reg32);
} }
/* Set Bus Master */ /* Set Bus Master */
@ -294,14 +274,11 @@ static void azalia_init(struct device *dev)
/* Wait 1ms */ /* Wait 1ms */
udelay(1000); udelay(1000);
// // Select Azalia mode. This needs to be controlled via devicetree.cb
reg8 = pci_read_config8(dev, 0x40); // Audio Control pci_or_config8(dev, 0x40, 1); // Audio Control
reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status // Docking not supported
reg8 &= ~(1 << 7); // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status
pci_write_config8(dev, 0x4d, reg8);
codec_mask = codec_detect(base); codec_mask = codec_detect(base);
@ -311,10 +288,7 @@ static void azalia_init(struct device *dev)
} }
/* Enable dynamic clock gating */ /* Enable dynamic clock gating */
reg8 = pci_read_config8(dev, 0x43); pci_update_config8(dev, 0x43, ~0x07, (1 << 2) | (1 << 0));
reg8 &= ~0x7;
reg8 |= (1 << 2) | (1 << 0);
pci_write_config8(dev, 0x43, reg8);
} }
static const char *azalia_acpi_name(const struct device *dev) static const char *azalia_acpi_name(const struct device *dev)

8
src/southbridge/intel/bd82x6x/bootblock.c
View file

@ -9,13 +9,7 @@
*/ */
static void enable_spi_prefetch(void) static void enable_spi_prefetch(void)
{ {
u8 reg8; pci_update_config8(PCH_LPC_DEV, BIOS_CNTL, ~(3 << 2), 2 << 2);
pci_devfn_t dev = PCH_LPC_DEV;
reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(3 << 2);
reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
pci_write_config8(dev, BIOS_CNTL, reg8);
} }
static void enable_port80_on_lpc(void) static void enable_port80_on_lpc(void)

4
src/southbridge/intel/bd82x6x/early_me.c
View file

@ -110,7 +110,6 @@ static inline void set_global_reset(int enable)
int intel_early_me_init_done(u8 status) int intel_early_me_init_done(u8 status)
{ {
u8 reset, errorcode, opmode; u8 reset, errorcode, opmode;
u16 reg16;
u32 mebase_l, mebase_h; u32 mebase_l, mebase_h;
u32 millisec; u32 millisec;
u32 hfs, me_fws2; u32 hfs, me_fws2;
@ -163,8 +162,7 @@ int intel_early_me_init_done(u8 status)
} else if ((me_fws2 & 0x100) == 0x100) { } else if ((me_fws2 & 0x100) == 0x100) {
if ((me_fws2 & 0x80) == 0x80) { if ((me_fws2 & 0x80) == 0x80) {
printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n"); printk(BIOS_NOTICE, "CPU was replaced & warm reset required...\n");
reg16 = pci_read_config16(PCI_DEV(0, 31, 0), 0xa2) & ~0x80; pci_and_config16(PCI_DEV(0, 31, 0), 0xa2, ~0x80);
pci_write_config16(PCI_DEV(0, 31, 0), 0xa2, reg16);
set_global_reset(0); set_global_reset(0);
system_reset(); system_reset();
} }

5
src/southbridge/intel/bd82x6x/early_thermal.c
View file

@ -38,7 +38,7 @@ void early_thermal_init(void)
pci_write_config32(dev, 0x44, 0x0); pci_write_config32(dev, 0x44, 0x0);
/* Activate temporary BAR. */ /* Activate temporary BAR. */
pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) | 5); pci_or_config32(dev, 0x40, 5);
write16p(TBARB_TEMP + 0x04, 0x3a2b); write16p(TBARB_TEMP + 0x04, 0x3a2b);
@ -61,7 +61,8 @@ void early_thermal_init(void)
write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0); write16p(TBARB_TEMP + 0x1a, (read16p(TBARB_TEMP + 0x1a) & ~0xf) | 0x10f0);
/* Disable temporary BAR */ /* Disable temporary BAR */
pci_write_config32(dev, 0x40, pci_read_config32(dev, 0x40) & ~1); pci_and_config32(dev, 0x40, ~1);
pci_write_config32(dev, 0x40, 0); pci_write_config32(dev, 0x40, 0);
write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c); write32(DEFAULT_RCBA + 0x38b0, (read32(DEFAULT_RCBA + 0x38b0) & 0xffff8003) | 0x403c);

13
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -417,22 +417,15 @@ static void pch_set_acpi_mode(void)
static void pch_disable_smm_only_flashing(struct device *dev) static void pch_disable_smm_only_flashing(struct device *dev)
{ {
u8 reg8;
printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
reg8 = pci_read_config8(dev, BIOS_CNTL);
reg8 &= ~(1 << 5); pci_and_config8(dev, BIOS_CNTL, ~(1 << 5));
pci_write_config8(dev, BIOS_CNTL, reg8);
} }
static void pch_fixups(struct device *dev) static void pch_fixups(struct device *dev)
{ {
u8 gen_pmcon_2;
/* Indicate DRAM init done for MRC S3 to know it can resume */ /* Indicate DRAM init done for MRC S3 to know it can resume */
gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2); pci_or_config8(dev, GEN_PMCON_2, 1 << 7);
gen_pmcon_2 |= (1 << 7);
pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
/* /*
* Enable DMI ASPM in the PCH * Enable DMI ASPM in the PCH

7
src/southbridge/intel/bd82x6x/me.c
View file

@ -438,7 +438,6 @@ static void intel_me7_finalize_smm(void)
{ {
struct me_hfs hfs; struct me_hfs hfs;
u32 reg32; u32 reg32;
u16 reg16;
mei_base_address = (u32 *) mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@ -461,10 +460,8 @@ static void intel_me7_finalize_smm(void)
mkhi_end_of_post(); mkhi_end_of_post();
/* Make sure IO is disabled */ /* Make sure IO is disabled */
reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
reg16 &= ~(PCI_COMMAND_MASTER | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
/* Hide the PCI device */ /* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1); RCBA32_OR(FD2, PCH_DISABLE_MEI1);

7
src/southbridge/intel/bd82x6x/me_8.x.c
View file

@ -432,7 +432,6 @@ void intel_me8_finalize_smm(void)
{ {
struct me_hfs hfs; struct me_hfs hfs;
u32 reg32; u32 reg32;
u16 reg16;
mei_base_address = (void *) mei_base_address = (void *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
@ -455,10 +454,8 @@ void intel_me8_finalize_smm(void)
mkhi_end_of_post(); mkhi_end_of_post();
/* Make sure IO is disabled */ /* Make sure IO is disabled */
reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); pci_and_config16(PCH_ME_DEV, PCI_COMMAND,
reg16 &= ~(PCI_COMMAND_MASTER | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16);
/* Hide the PCI device */ /* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1); RCBA32_OR(FD2, PCH_DISABLE_MEI1);

19
src/southbridge/intel/bd82x6x/pch.c
View file

@ -301,7 +301,6 @@ static void pch_pcie_devicetree_update(
static void pch_pcie_enable(struct device *dev) static void pch_pcie_enable(struct device *dev)
{ {
struct southbridge_intel_bd82x6x_config *config = dev->chip_info; struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
u16 reg16;
if (!config) if (!config)
return; return;
@ -345,9 +344,7 @@ static void pch_pcie_enable(struct device *dev)
/* Handle workaround for PPT and CPT/B1+ */ /* Handle workaround for PPT and CPT/B1+ */
if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) && if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B1) &&
!pch_pcie_check_set_enabled(dev)) { !pch_pcie_check_set_enabled(dev)) {
u8 reg8 = pci_read_config8(dev, 0xe2); pci_or_config8(dev, 0xe2, 1);
reg8 |= 1;
pci_write_config8(dev, 0xe2, reg8);
} }
/* /*
@ -358,10 +355,8 @@ static void pch_pcie_enable(struct device *dev)
} }
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg16 = pci_read_config16(dev, PCI_COMMAND); pci_and_config16(dev, PCI_COMMAND,
reg16 &= ~(PCI_COMMAND_MASTER | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config16(dev, PCI_COMMAND, reg16);
/* Do not claim downstream transactions for PCIe ports */ /* Do not claim downstream transactions for PCIe ports */
new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn));
@ -408,8 +403,6 @@ static void pch_pcie_enable(struct device *dev)
void pch_enable(struct device *dev) void pch_enable(struct device *dev)
{ {
u16 reg16;
/* PCH PCIe Root Ports get special handling */ /* PCH PCIe Root Ports get special handling */
if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT)
return pch_pcie_enable(dev); return pch_pcie_enable(dev);
@ -418,10 +411,8 @@ void pch_enable(struct device *dev)
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg16 = pci_read_config16(dev, PCI_COMMAND); pci_and_config16(dev, PCI_COMMAND,
reg16 &= ~(PCI_COMMAND_MASTER | ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide this device if possible */ /* Hide this device if possible */
pch_hide_devfn(dev->path.pci.devfn); pch_hide_devfn(dev->path.pci.devfn);

18
src/southbridge/intel/bd82x6x/pci.c
View file

@ -11,30 +11,22 @@
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
{ {
u16 reg16; u16 reg16;
u8 reg8;
printk(BIOS_DEBUG, "PCI init.\n"); printk(BIOS_DEBUG, "PCI init.\n");
/* Enable Bus Master */ /* Enable Bus Master */
reg16 = pci_read_config16(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg16 |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, reg16);
/* This device has no interrupt */ /* This device has no interrupt */
pci_write_config8(dev, INTR, 0xff); pci_write_config8(dev, INTR, 0xff);
/* disable parity error response and SERR */ /* disable parity error response and SERR */
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); pci_and_config16(dev, PCI_BRIDGE_CONTROL,
reg16 &= ~PCI_BRIDGE_CTL_PARITY; ~(PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR));
reg16 &= ~PCI_BRIDGE_CTL_SERR;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
/* Master Latency Count must be set to 0x04! */ /* Master Latency Count must be set to 0x04! */
reg8 = pci_read_config8(dev, SMLT); pci_update_config8(dev, SMLT, 0x07, (0x04 << 3));
reg8 &= 0x07;
reg8 |= (0x04 << 3);
pci_write_config8(dev, SMLT, reg8);
/* Clear errors in status registers */ /* Clear errors in status registers. FIXME: do we need to do something? */
reg16 = pci_read_config16(dev, PSTS); reg16 = pci_read_config16(dev, PSTS);
//reg16 |= 0xf900; //reg16 |= 0xf900;
pci_write_config16(dev, PSTS, reg16); pci_write_config16(dev, PSTS, reg16);

52
src/southbridge/intel/bd82x6x/pcie.c
View file

@ -109,9 +109,7 @@ static void pch_pcie_pm_early(struct device *dev)
pci_write_config8(dev, 0xe1, reg8); pci_write_config8(dev, 0xe1, reg8);
/* Set 0xE8[0] = 1 */ /* Set 0xE8[0] = 1 */
reg32 = pci_read_config32(dev, 0xe8); pci_or_config32(dev, 0xe8, 1);
reg32 |= 1;
pci_write_config32(dev, 0xe8, reg32);
/* Adjust Common Clock exit latency */ /* Adjust Common Clock exit latency */
reg32 = pci_read_config32(dev, 0xd8); reg32 = pci_read_config32(dev, 0xd8);
@ -144,38 +142,24 @@ static void pch_pcie_pm_late(struct device *dev)
{ {
struct southbridge_intel_bd82x6x_config *config = dev->chip_info; struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
enum aspm_type apmc = 0; enum aspm_type apmc = 0;
u32 reg32;
/* Set 0x314 = 0x743a361b */ /* Set 0x314 = 0x743a361b */
pci_write_config32(dev, 0x314, 0x743a361b); pci_write_config32(dev, 0x314, 0x743a361b);
/* Set 0x318[31:16] = 0x1414 */ /* Set 0x318[31:16] = 0x1414 */
reg32 = pci_read_config32(dev, 0x318); pci_update_config32(dev, 0x318, 0x0000ffff, 0x14140000);
reg32 &= 0x0000ffff;
reg32 |= 0x14140000;
pci_write_config32(dev, 0x318, reg32);
/* Set 0x324[5] = 1 */ /* Set 0x324[5] = 1 */
reg32 = pci_read_config32(dev, 0x324); pci_or_config32(dev, 0x324, 1 << 5);
reg32 |= (1 << 5);
pci_write_config32(dev, 0x324, reg32);
/* Set 0x330[7:0] = 0x40 */ /* Set 0x330[7:0] = 0x40 */
reg32 = pci_read_config32(dev, 0x330); pci_update_config32(dev, 0x330, ~0xff, 0x40);
reg32 &= ~(0xff);
reg32 |= 0x40;
pci_write_config32(dev, 0x330, reg32);
/* Set 0x33C[24:0] = 0x854c74 */ /* Set 0x33C[24:0] = 0x854c74 */
reg32 = pci_read_config32(dev, 0x33c); pci_update_config32(dev, 0x33c, 0xff000000, 0x00854c74);
reg32 &= 0xff000000;
reg32 |= 0x00854c74;
pci_write_config32(dev, 0x33c, reg32);
/* No IO-APIC, Disable EOI forwarding */ /* No IO-APIC, Disable EOI forwarding */
reg32 = pci_read_config32(dev, 0xd4); pci_or_config32(dev, 0xd4, 1 << 1);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xd4, reg32);
/* Check for a rootport ASPM override */ /* Check for a rootport ASPM override */
switch (PCI_FUNC(dev->path.pci.devfn)) { switch (PCI_FUNC(dev->path.pci.devfn)) {
@ -207,19 +191,15 @@ static void pch_pcie_pm_late(struct device *dev)
/* Setup the override or get the real ASPM setting */ /* Setup the override or get the real ASPM setting */
if (apmc) { if (apmc) {
reg32 = pci_read_config32(dev, 0xd4); pci_or_config32(dev, 0xd4, (apmc << 2) | (1 << 4));
reg32 |= (apmc << 2) | (1 << 4);
pci_write_config32(dev, 0xd4, reg32);
} else { } else {
apmc = pci_read_config32(dev, 0x50) & 3; apmc = pci_read_config32(dev, 0x50) & 3;
} }
/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
if (apmc == PCIE_ASPM_BOTH) { if (apmc == PCIE_ASPM_BOTH)
reg32 = pci_read_config32(dev, 0xe8); pci_or_config32(dev, 0xe8, 1 << 1);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xe8, reg32);
}
} }
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
@ -236,10 +216,8 @@ static void pci_init(struct device *dev)
// This has no effect but the OS might expect it // This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10); pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); pci_update_config16(dev, PCI_BRIDGE_CONTROL,
reg16 &= ~PCI_BRIDGE_CTL_PARITY; ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA);
reg16 |= PCI_BRIDGE_CTL_NO_ISA;
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG #ifdef EVEN_MORE_DEBUG
u32 reg32; u32 reg32;
@ -253,7 +231,7 @@ static void pci_init(struct device *dev)
printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
#endif #endif
/* Clear errors in status registers */ /* Clear errors in status registers. FIXME: Do something? */
reg16 = pci_read_config16(dev, 0x06); reg16 = pci_read_config16(dev, 0x06);
//reg16 |= 0xf900; //reg16 |= 0xf900;
pci_write_config16(dev, 0x06, reg16); pci_write_config16(dev, 0x06, reg16);
@ -264,9 +242,7 @@ static void pci_init(struct device *dev)
/* Enable expresscard hotplug events. */ /* Enable expresscard hotplug events. */
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
pci_write_config32(dev, 0xd8, pci_or_config32(dev, 0xd8, 1 << 30);
pci_read_config32(dev, 0xd8)
| (1 << 30));
pci_write_config16(dev, 0x42, 0x142); pci_write_config16(dev, 0x42, 0x142);
} }
} }

17
src/southbridge/intel/bd82x6x/sata.c
View file

@ -138,8 +138,7 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, 0x92, reg16); pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ /* SATA Initialization register */
pci_write_config32(dev, 0x94, pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
/* Initialize AHCI memory-mapped space */ /* Initialize AHCI memory-mapped space */
abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5); abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
@ -172,9 +171,7 @@ static void sata_init(struct device *dev)
/* IDE */ /* IDE */
/* Without AHCI BAR no memory decoding */ /* Without AHCI BAR no memory decoding */
reg16 = pci_read_config16(dev, PCI_COMMAND); pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
reg16 &= ~PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, reg16);
if (sata_mode == 1) { if (sata_mode == 1) {
/* Native mode on both primary and secondary. */ /* Native mode on both primary and secondary. */
@ -182,7 +179,7 @@ static void sata_init(struct device *dev)
printk(BIOS_DEBUG, "SATA: Controller in IDE compat mode.\n"); printk(BIOS_DEBUG, "SATA: Controller in IDE compat mode.\n");
} else { } else {
/* Legacy mode on both primary and secondary. */ /* Legacy mode on both primary and secondary. */
pci_update_config8(dev, 0x09, ~0x05, 0x00); pci_and_config8(dev, 0x09, ~0x05);
printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n"); printk(BIOS_DEBUG, "SATA: Controller in IDE legacy mode.\n");
} }
@ -191,14 +188,10 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
/* Port enable + OOB retry mode */ /* Port enable + OOB retry mode */
reg16 = pci_read_config16(dev, 0x92); pci_update_config16(dev, 0x92, ~0x3f, config->sata_port_map | 0x8000);
reg16 &= ~0x3f;
reg16 |= config->sata_port_map | 0x8000;
pci_write_config16(dev, 0x92, reg16);
/* SATA Initialization register */ /* SATA Initialization register */
pci_write_config32(dev, 0x94, pci_write_config32(dev, 0x94, ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
} }
/* Set Gen3 Transmitter settings if needed */ /* Set Gen3 Transmitter settings if needed */

1
src/southbridge/intel/bd82x6x/smbus.c
View file

@ -15,6 +15,7 @@ static void pch_smbus_init(struct device *dev)
u16 reg16; u16 reg16;
/* Enable clock gating */ /* Enable clock gating */
/* FIXME: Using 32-bit ops with a 16-bit variable is a bug! These should be 16-bit! */
reg16 = pci_read_config32(dev, 0x80); reg16 = pci_read_config32(dev, 0x80);
reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
pci_write_config32(dev, 0x80, reg16); pci_write_config32(dev, 0x80, reg16);

21
src/southbridge/intel/bd82x6x/smihandler.c
View file

@ -99,15 +99,15 @@ static void xhci_sleep(u8 slp_typ)
switch (slp_typ) { switch (slp_typ) {
case ACPI_S3: case ACPI_S3:
case ACPI_S4: case ACPI_S4:
/* FIXME: Unbalanced width in read/write ops (16-bit read then 32-bit write) */
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74);
reg16 &= ~0x03UL; reg16 &= ~0x03UL;
pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); pci_write_config32(PCH_XHCI_DEV, 0x74, reg16);
pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND,
PCI_COMMAND_MEMORY); PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
xhci_bar = pci_read_config32(PCH_XHCI_DEV, xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL;
PCI_BASE_ADDRESS_0) & ~0xFUL;
if ((xhci_bar + 0x4C0) & 1) if ((xhci_bar + 0x4C0) & 1)
pch_iobp_update(0xEC000082, ~0UL, (3 << 2)); pch_iobp_update(0xEC000082, ~0UL, (3 << 2));
@ -118,19 +118,14 @@ static void xhci_sleep(u8 slp_typ)
if ((xhci_bar + 0x4F0) & 1) if ((xhci_bar + 0x4F0) & 1)
pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); pch_iobp_update(0xEC000382, ~0UL, (3 << 2));
reg16 = pci_read_config16(PCH_XHCI_DEV, PCI_COMMAND); pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND,
reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
pci_write_config16(PCH_XHCI_DEV, PCI_COMMAND, reg16);
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); pci_or_config16(PCH_XHCI_DEV, 0x74, 0x03);
reg16 |= 0x03;
pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
break; break;
case ACPI_S5: case ACPI_S5:
reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); pci_or_config16(PCH_XHCI_DEV, 0x74, (1 << 8) | 0x03);
reg16 |= ((1 << 8) | 0x03);
pci_write_config16(PCH_XHCI_DEV, 0x74, reg16);
break; break;
} }
} }

4
src/southbridge/intel/bd82x6x/usb_xhci.c
View file

@ -20,9 +20,7 @@ static void usb_xhci_init(struct device *dev)
pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping); pci_write_config32(dev, XOCM, config->xhci_overcurrent_mapping);
/* lock overcurrent map */ /* lock overcurrent map */
reg32 = pci_read_config32(dev, 0x44); pci_or_config32(dev, 0x44, 1);
reg32 |= 1;
pci_write_config32(dev, 0x44, reg32);
pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports); pci_write_config32(dev, XUSB2PRM, config->xhci_switchable_ports);
pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports); pci_write_config32(dev, USB3PRM, config->superspeed_capable_ports);