skylake: Add GPIO macro for configuring inverted APIC input
Add a GPIO macro that allows a pin to be routed to the APIC with the input inverted. This allows a normal interrupt to get used as a GPE during firmware and still be used as a perhiperal interrupt in the kernel. BUG=chrome-os-partner:58666 TEST=boot en eve and use TPM IRQ in firmware and OS Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17176 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -144,6 +144,12 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
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_PAD_CFG(pad_, term_, \
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_PAD_CFG(pad_, term_, \
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_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
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_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
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/* General purpose input passed through to IOxAPIC as inverted input. */
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#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \
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_PAD_CFG(pad_, term_, \
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_DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, \
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YES))
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/* General purpose input routed to SCI. This assumes edge triggered events. */
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/* General purpose input routed to SCI. This assumes edge triggered events. */
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#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
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#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
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_PAD_CFG_ATTRS(pad_, term_, \
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_PAD_CFG_ATTRS(pad_, term_, \
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