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mb/google/brask/var/constitution: Add TcssAuxori for constitution 

Enable SBU orientation handling by SoC for both USBC port2 and USBC
port3.
Constitution USBC port1 has retimer but USBC port2 and USBC port3 don't,
they do not flip the data lines, hence we need to set bits for USBC ports.

Change-Id: I4c5dfdba6c38c6e2f308b281ed316bb687ad8d8b
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Morris Hsu 2023-03-24 14:06:07 +08:00 committed by Lean Sheng Tan
parent ac69ce9122
commit c826c11b50
1 changed files with 12 additions and 0 deletions
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12
src/mainboard/google/brya/variants/constitution/overridetree.cb
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@ -5,6 +5,18 @@ chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled" register "sagv" = "SaGv_Enabled"
# SOC Aux orientation override:
# This is a bitfield that corresponds to up to 4 TCSS ports.
# Bits (0,1) allocated for TCSS Port1 configuration, Bits (2,3)for TCSS Port2, Bits (4,5)for TCSS Port3.
# TcssAuxOri = 010100b
# Bit0,Bit2,Bit4 set to "1" indicates no retimer on USBC Ports, otherwise is "0"
# Bit1,Bit3,Bit5 set to "0" indicates Aux lines are not swapped on the
# motherboard to USBC connector
register "tcss_aux_ori" = "0x14"
register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}"
register "typec_aux_bias_pads[2]" = "{.pad_auxp_dc = GPP_A19, .pad_auxn_dc = GPP_A20}"
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # HDMI-IN register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # HDMI-IN
register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4 register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port 4
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5 register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5