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pcengines/apu1: Fix SPD for 4GB model 

Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.

Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki 2015-10-14 16:03:56 +03:00
parent f50603176b
commit c82ab0adf5
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex
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@ -127,7 +127,8 @@
# 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
# 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
# 0x500 = 160ns - for 2 Gigabit chips # 0x500 = 160ns - for 2 Gigabit chips
00 05 # 0x820 = 260ns - for 4 Gigabit chips
20 08
# 26 Minimum Internal Write to Read Command Delay Time (tWTRmin) # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
# 0x3c = 7.5 ns - All DDR3 SDRAM speed bins # 0x3c = 7.5 ns - All DDR3 SDRAM speed bins