pcengines/apu1: Fix SPD for 4GB model

Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.

Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/pcengines/apu1/HYNIX-H5TQ4G83MFR.spd.hex

@@ -127,7 +127,8 @@
 # 24 Minimum Refresh Recovery Delay Time (tRFCmin), LSB
 # 25 Minimum Refresh Recovery Delay Time (tRFCmin), MSB
 #    0x500 = 160ns - for 2 Gigabit chips
-00 05
+#    0x820 = 260ns - for 4 Gigabit chips
+20 08
 
 # 26 Minimum Internal Write to Read Command Delay Time (tWTRmin)
 #    0x3c = 7.5 ns - All DDR3 SDRAM speed bins