qualcomm/qcs405: enable SPI bus 4 for TPM

Change-Id: Ic282daf10dad42bc4513cc55f15ce80a4bd316a5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Prudhvi Yarlagadda <pyarlaga@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/mistral/Makefile.inc

@@ -7,6 +7,7 @@ bootblock-y += bootblock.c
 verstage-y += memlayout.ld
 verstage-y += chromeos.c
 verstage-y += reset.c
+verstage-y += verstage.c
 
 romstage-y += memlayout.ld
 romstage-y += chromeos.c

src/mainboard/google/mistral/verstage.c

@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <console/console.h>
+#include <security/vboot/vboot_common.h>
+#include <soc/clock.h>
+#include <spi-generic.h>
+
+void verstage_mainboard_init(void)
+{
+	struct spi_slave spi;
+
+	printk(BIOS_ERR, "Trying to initialize TPM SPI bus\n");
+	if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS,
+			    CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) {
+		printk(BIOS_ERR, "Failed to setup TPM SPI slave\n");
+	}
+}