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mb/google/sarien/variants/sarien: Add GPIO H3 for DVT1 

Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1.

BUG=b:123461432
TEST=Built and tested on sarien system

Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
John Su 2019-02-12 11:44:49 +08:00 committed by Patrick Georgi
parent 025c575750
commit c8464748cd
1 changed files with 1 additions and 1 deletions
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src/mainboard/google/sarien/variants/sarien/gpio.c
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@ -188,7 +188,7 @@ static const struct pad_config gpio_table[] = {
/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SCLK */ PAD_NC(GPP_H0, NONE),
/* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */ /* I2S2_SFRM */ PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */
/* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */ /* I2S2_TXD */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */
/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), /* I2S2_RXD */ PAD_CFG_GPI(GPP_H3, NONE, DEEP), /* CNVI_EN# */
/* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */ /* I2C2_SDA */ PAD_NC(GPP_H4, NONE), /* T388 */
/* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */ /* I2C2_SCL */ PAD_NC(GPP_H5, NONE), /* T389 */
/* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */ /* I2C3_SDA */ PAD_NC(GPP_H6, NONE), /* T378 */