mb/google/brya: Add PEG and initial Nvidia dGPU ASL support
Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Tim Wawrzynczak
parent
2efd8315f2
commit
c852533379
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@ -264,4 +264,9 @@ config MEMORY_SOLDERDOWN
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config HAVE_SLP_S0_GATE
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def_bool n
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config INCLUDE_NVIDIA_GPU_ASL
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def_bool n
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help
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Select this if the variant has an Nvidia GN20 GPU attached to PEG1
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endif # BOARD_GOOGLE_BRYA_COMMON
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@ -0,0 +1,44 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define NV_ERROR_SUCCESS 0x0
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#define NV_ERROR_UNSPECIFIED 0x80000001
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#define NV_ERROR_UNSUPPORTED 0x80000002
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#define PCI_OWNER_SBIOS 0x0
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#define PCI_OWNER_DRIVER 0x1
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#define OPTIMUS_POWER_CONTROL_DISABLE 0x2
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#define OPTIMUS_POWER_CONTROL_ENABLE 0x3
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#define OPTIMUS_CONTROL_NO_RUN_PS0 0x0
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#define OPTIMUS_CONTROL_RUN_PS0 0x1
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#define GC6_STATE_EXITED 0x0
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#define GC6_STATE_ENTERED 0x1
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#define GC6_STATE_TRANSITION 0x2
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#define GC6_DEFER_DISABLE 0x0
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#define GC6_DEFER_ENABLE 0x1
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#define NOTIFY_GPS_EVENT_STATUS_CHANGE 0xc0
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#define NOTIFY_GPS_NVPCF_STATUS_CHANGE 0xc5
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#define NOTIFY_GPS_EVENT_LIMIT_POWER_0 0xd1
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#define NOTIFY_GPS_EVENT_LIMIT_POWER_1 0xd2
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#define NOTIFY_GPS_EVENT_LIMIT_POWER_2 0xd3
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#define NOTIFY_GPS_EVENT_LIMIT_POWER_3 0xd4
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#define NOTIFY_GPS_EVENT_LIMIT_POWER_4 0xd5
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/* Defines for NVJT subfunction */
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#define NVJT_GPC_GSS 0
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#define NVJT_GPC_EGNS 1
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#define NVJT_GPC_EGIS 2
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#define NVJT_GPS_XGXS 3
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#define NVJT_GPS_XGIS 4
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#define UUID_NVOP "a486d8f8-0bda-471b-a72b-6042a6b5bee0"
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#define UUID_NVJT "cbeca351-067b-4924-9cbd-b46b00b86f34"
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#define UUID_NBCI "d4a50b75-65c7-46f7-bfb7-41514cea0244"
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#define REVISION_MIN_NVOP 0x100
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#define REVISION_MIN_NVJT 0x100
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#define REVISION_MIN_NBCI 0x102
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@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include "gpu_defines.h"
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Scope (\_SB.PCI0.PEG0)
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{
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#include "peg.asl"
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Device (PEGP)
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{
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Name (_ADR, 0x0)
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OperationRegion (PCIC, PCI_Config, 0x00, 0x100)
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Field (PCIC, DWordAcc, NoLock, Preserve)
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{
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NVID, 16,
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NDID, 16,
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CMDR, 8,
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VGAR, 2008, /* VGA Registers */
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}
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#include "utility.asl"
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#include "power.asl"
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#include "nvop.asl"
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#include "nvjt.asl"
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Method (_DSM, 4, Serialized)
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{
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If (Arg0 == ToUUID (UUID_NVOP))
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{
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If (ToInteger(Arg1) >= REVISION_MIN_NVOP)
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{
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Return (NVOP (Arg2, Arg3))
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}
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}
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ElseIf (Arg0 == ToUUID (UUID_NVJT))
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{
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If (ToInteger (Arg1) >= REVISION_MIN_NVJT)
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{
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Return (NVJT (Arg2, Arg3))
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}
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}
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Return (NV_ERROR_UNSUPPORTED)
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}
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}
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}
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@ -0,0 +1,129 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define JT_FUNC_SUPPORT 0
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#define JT_FUNC_CAPS 1
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#define JT_FUNC_POWERCONTROL 2
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#define JT_FUNC_PLATPOLICY 3
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Method (NVJT, 2, Serialized)
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{
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Switch (ToInteger(Arg0))
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{
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Case (JT_FUNC_SUPPORT)
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{
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Return (ITOB(
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(1 << JT_FUNC_SUPPORT) |
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(1 << JT_FUNC_CAPS) |
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(1 << JT_FUNC_POWERCONTROL) |
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(1 << JT_FUNC_PLATPOLICY)))
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}
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Case (JT_FUNC_CAPS)
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{
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Return (ITOB(
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(0 << 0) | /* JTE: G-Sync NVSR Power Features Enabled */
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(1 << 0) | /* NVSE: NVSR Disabled */
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(0 << 3) | /* PPR: Panel Power Rail */
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(0 << 5) | /* SRPR: Self-Refresh Controller Power Rail */
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(0 << 6) | /* FBPR: FB Power Rail */
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(0 << 8) | /* GPR: GPU Power Rail */
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(0 << 10) | /* GCR: GC6 ROM */
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(1 << 11) | /* PTH: No SMI Handler */
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(0 << 12) | /* NOT: Supports Notify on GC6 State done */
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(1 << 13) | /* MHYB: MS Hybrid Support (deferred GC6) */
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(0 << 14) | /* RPC: Root Port Control */
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(0 << 15) | /* GC6 Version (GC6-E) */
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(0 << 17) | /* GEI: GC6 Exit ISR Support */
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(0 << 18) | /* GSW: GC6 Self Wakeup */
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(0x200 << 20))) /* MXRV: Highest Revision */
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}
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Case (JT_FUNC_POWERCONTROL)
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{
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CreateField (Arg1, 0, 3, GPC) /* GPU Power Control */
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CreateField (Arg1, 4, 1, PPC) /* Panel Power Control */
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CreateField (Arg1, 14, 2, DFGC) /* Defer GC6 enter/exit */
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CreateField (Arg1, 16, 3, GPCX) /* Deferred GC6 exit */
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/* Deferred GC6 entry/exit is requested */
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If (ToInteger(GPC) != 0 || ToInteger(DFGC) != 0)
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{
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DFEN = ToInteger(DFGC)
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DFCI = ToInteger(GPC)
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DFCO = ToInteger(GPCX)
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}
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Local0 = Buffer (4) { 0x0 }
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CreateField (Local0, 0, 3, CGCS) /* Current GC State */
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CreateField (Local0, 3, 1, CGPS) /* Current GPU power status */
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CreateField (Local0, 7, 1, CPSS) /* Current panel and SRC state */
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/* Leave early if deferred GC6 is requested */
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If (DFEN != 0)
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{
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CGCS = 1
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CGPS = 1
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Return (Local0)
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}
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Switch (ToInteger(GPC))
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{
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/* Get GCU GCx Sleep Status */
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Case (NVJT_GPC_GSS)
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{
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If (^_STA () != 0)
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{
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CGPS = 1
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CGCS = 1
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}
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Else
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{
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CGPS = 0
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CGCS = 3
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}
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}
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Case (NVJT_GPC_EGNS)
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{
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/* Enter GC6; no self-refresh */
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GC6I ()
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CPSS = 1
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CGCS = 0
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}
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Case (NVJT_GPC_EGIS)
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{
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/* Enter GC6; enable self-refresh */
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GC6I ()
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If (ToInteger (PPC) == 0)
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{
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CPSS = 0
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}
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CGCS = 0
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}
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Case (NVJT_GPS_XGXS)
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{
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/* Exit GC6; stop self-refresh */
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GC6O ()
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CGCS = 1
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CGPS = 1
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If (ToInteger (PPC) != 0)
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{
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CPSS = 0
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}
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}
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Case (NVJT_GPS_XGIS)
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{
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/* Exit GC6 for self-refresh */
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GC6O ()
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CGCS = 1
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CGPS = 1
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If (ToInteger (PPC) != 0)
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{
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CPSS = 0
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}
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}
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}
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Return (Local0)
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}
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}
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Return (NV_ERROR_UNSUPPORTED)
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}
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@ -0,0 +1,69 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#define NVOP_FUNC_SUPPORT 0x00
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#define NVOP_FUNC_GET_OBJ_BY_TYPE 0x10
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#define NVOP_FUNC_OPTIMUS_CAPS 0x1a
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#define NVOP_FUNC_OPTIMUS_STATUS 0x1b
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Method (NVOP, 2, Serialized)
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{
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Switch (ToInteger (Arg0))
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{
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Case (NVOP_FUNC_SUPPORT)
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{
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Return (ITOB (
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(1 << NVOP_FUNC_SUPPORT) |
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(1 << NVOP_FUNC_OPTIMUS_CAPS) |
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(1 << NVOP_FUNC_OPTIMUS_STATUS)))
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}
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Case (NVOP_FUNC_OPTIMUS_CAPS)
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{
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CreateField(Arg1, 0, 1, FLUP) /* Flag Update */
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CreateField(Arg1, 1, 1, CSOT) /* Change configuration Space Owner Target */
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CreateField(Arg1, 2, 1, CSOW) /* Change configuration Space Owner Write */
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CreateField(Arg1, 24, 2, NPCE) /* New Power Control Enable setting */
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/* Change Optimus power control capabilities */
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If (ToInteger (FLUP) != 0 && ToInteger (NPCE) != 0)
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{
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OPCS = NPCE
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}
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/* Change PCI configuration space save/restore owner */
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If (ToInteger (CSOW) == 1)
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{
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PCIO = CSOT
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}
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/* Current GPU Control Status */
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If (\_SB.PCI0.PEG0.PGPR._STA == 1)
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{
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Local0 = 3
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}
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Else
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{
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Local0 = 0
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}
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Return (ITOB (
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(1 << 0) | /* Optimus Enabled */
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(Local0 << 3) | /* Current GPU Control Status */
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(0 << 6) | /* Shared Discrete GPU Hotplug Capabilities */
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(0 << 7) | /* MUXed DDC/Aux Capabilities */
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(PCIO << 8) | /* PCIe Configuration Space Owner */
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(1 << 24) | /* Platform Optimus Power Capabilities */
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(0 << 27))) /* Optimus HD Audio Codec Capabilities */
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}
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Case (NVOP_FUNC_OPTIMUS_STATUS)
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{
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Return (ITOB (
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(0 << 0) | /* Optimus Audio Codec Control */
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(0 << 2) | /* Request GPU Power State */
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(0 << 4) | /* Evaluate Requested GPU Power State */
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(0 << 5) | /* Request Optimus Adapter Policy */
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(0 << 7))) /* Evaluate Requested Optimus Adapter Selection */
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}
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}
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Return (NV_ERROR_UNSUPPORTED)
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}
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@ -0,0 +1,95 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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External (\_SB.PCI0.DGPU, DeviceObj)
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External (\_SB.PCI0.PEG0.PEGP._OFF, MethodObj)
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External (\_SB.PCI0.PEG0.PEGP._ON, MethodObj)
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OperationRegion (PCIC, PCI_Config, 0x00, 0x100)
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Field (PCIC, AnyAcc, NoLock, Preserve)
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{
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Offset (0x52),
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, 13,
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LASX, 1, /* Link Active Status */
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Offset (0xe0),
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, 7,
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NCB7, 1, /* Scratch bit to save L2/3 state */
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Offset (0xe2),
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, 2,
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L23E, 1, /* L23_Rdy Entry request */
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L23R, 1 /* L23_Rdy Detect Transition */
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}
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/* L2/3 Entry sequence */
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Method (DL23, 0, Serialized)
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{
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L23E = 1
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Local0 = 8
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While (Local0 > 0)
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{
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If (!L23E)
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{
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Break
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}
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Sleep (16)
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Local0--
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}
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NCB7 = 1
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}
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/* L2/3 exit seqeuence */
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Method (LD23, 0, Serialized)
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{
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If (!NCB7)
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{
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Return
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}
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L23R = 1
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Local0 = 20
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While (Local0 > 0)
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{
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If (!L23R)
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{
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Break
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}
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Sleep (16)
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Local0--
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}
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NCB7 = 0
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Local0 = 8
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While (Local0 > 0)
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{
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If (LASX == 1)
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{
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Break
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}
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Sleep (16)
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Local0--
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}
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}
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/* PEG Power Resource */
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PowerResource (PGPR, 0, 0)
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{
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Method (_ON, 0, Serialized)
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{
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/* Power up GPU from GCOFF (or GC6 exit if deferred) */
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\_SB.PCI0.PEG0.PEGP._ON ()
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_STA = 1
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}
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Method (_OFF, 0, Serialized)
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{
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/* Power down GPU to GCOFF (or GC6 entry if deferred) */
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_STA = 0
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\_SB.PCI0.PEG0.PEGP._OFF ()
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}
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Name (_STA, 0)
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}
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Name (_PR0, Package() { PGPR })
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Name (_PR2, Package() { PGPR })
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Name (_PR3, Package() { PGPR })
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@ -0,0 +1,297 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Voltage rail control signals */
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#define GPIO_1V8_PWR_EN GPP_E18
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#define GPIO_1V8_PG GPP_E20
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#define GPIO_NV33_PWR_EN GPP_A21
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#define GPIO_NV33_PG GPP_A22
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#define GPIO_NVVDD_PWR_EN GPP_E0
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#define GPIO_NVVDD_PG GPP_E16
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#define GPIO_PEXVDD_PWR_EN GPP_E10
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#define GPIO_PEXVDD_PG GPP_E17
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#define GPIO_FBVDD_PWR_EN GPP_A17
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#define GPIO_FBVDD_PG GPP_E4
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#define GPIO_GPU_PERST_L GPP_B3
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#define GPIO_GPU_ALLRAILS_PG GPP_E5
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#define GPIO_GPU_NVVDD_EN GPP_A19
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#define GC6_DEFER_TYPE_EXIT_GC6 3
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/* Optimus Power Control State */
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Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE)
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/* PCI configuration space Owner */
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Name (PCIO, PCI_OWNER_SBIOS)
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/* Saved PCI configuration space memory (VGA Buffer) */
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Name (VGAB, Buffer (0xfb) { 0x00 })
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/* Deferred GPU State */
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Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0)
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/* GC6 Entry/Exit state */
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Name (GC6E, GC6_STATE_EXITED)
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/* Defer GC6 entry / exit until D3-cold request */
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Name (DFEN, 0)
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/* Deferred GC6 Enter control */
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Name (DFCI, 0)
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/* Deferred GC6 Exit control */
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Name (DFCO, 0)
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/* "GC6 In", i.e. GC6 Entry Sequence */
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Method (GC6I, 0, Serialized)
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{
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GC6E = GC6_STATE_TRANSITION
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/* Put PCIe link into L2/3 */
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\_SB.PCI0.PEG0.DL23 ()
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/* Assert GPU_PERST_L */
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\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
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/* Deassert PG_GPU_ALLRAILS */
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\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
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/* Deassert EN_PP0950_GPU_X */
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\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
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/* Wait for de-assertion of PG_PP0950_GPU */
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GPPL (GPIO_PEXVDD_PG, 0, 20)
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/* Deassert EN_PPVAR_GPU_NVVDD */
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\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
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/* Wait for de-assertion of PG_PPVAR_GPU_NVVDD */
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GPPL (GPIO_NVVDD_PG, 0, 20)
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/* Deassert EN_PCH_PPVAR_GPU_FBVDDQ */
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\_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN)
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|
||||
/* Deassert EN_PP3300_GPU */
|
||||
\_SB.PCI0.CTXS (GPIO_NV33_PWR_EN)
|
||||
|
||||
/* Wait for de-assertion of PG_PP3300_GPU */
|
||||
GPPL (GPIO_NV33_PG, 0, 20)
|
||||
|
||||
GC6E = GC6_STATE_ENTERED
|
||||
}
|
||||
|
||||
/* "GC6 Out", i.e. GC6 Exit Sequence */
|
||||
Method (GC6O, 0, Serialized)
|
||||
{
|
||||
GC6E = GC6_STATE_TRANSITION
|
||||
|
||||
/* Assert EN_PP3300_GPU */
|
||||
\_SB.PCI0.STXS (GPIO_NV33_PWR_EN)
|
||||
|
||||
/* Wait for assertion of PG_PP3300_GPU */
|
||||
GPPL (GPIO_NV33_PG, 1, 20)
|
||||
|
||||
/* Deassert GPU_PERST_L */
|
||||
\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
|
||||
|
||||
/* Put PCIe link into L0 state */
|
||||
\_SB.PCI0.PEG0.LD23 ()
|
||||
|
||||
/* Wait for GPU to assert GPU_NVVDD_EN */
|
||||
GPPL (GPIO_GPU_NVVDD_EN, 1, 20)
|
||||
|
||||
/*
|
||||
* There is a 4ms window once the GPU asserts GPU_NVVDD_EN to
|
||||
* perform the following:
|
||||
* 1. Enable GPU_NVVDD
|
||||
* 2. Enable GPU_PEX
|
||||
* 3. Wait for all PG
|
||||
* 4. Assert FBVDD
|
||||
* At the end of the 4ms window, the GPU will deassert its
|
||||
* GPIO1_GC6_FB_EN signal that is used to keep the FBVDD
|
||||
* rail up during GC6.
|
||||
*/
|
||||
\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
|
||||
Stall (20)
|
||||
\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
|
||||
GPPL (GPIO_NVVDD_PG, 1, 4)
|
||||
GPPL (GPIO_PEXVDD_PG, 1, 4)
|
||||
\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
|
||||
|
||||
/* Assert PG_GPU_ALLRAILS */
|
||||
\_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG)
|
||||
|
||||
GC6E = GC6_STATE_EXITED
|
||||
}
|
||||
|
||||
/* GCOFF exit sequence */
|
||||
Method (PGON, 0, Serialized)
|
||||
{
|
||||
/* Assert PERST# */
|
||||
\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
|
||||
|
||||
/* Ramp up 1.8V rail */
|
||||
\_SB.PCI0.STXS (GPIO_1V8_PWR_EN)
|
||||
GPPL (GPIO_1V8_PG, 1, 20)
|
||||
|
||||
/* Ramp up NV33 rail */
|
||||
\_SB.PCI0.STXS (GPIO_NV33_PWR_EN)
|
||||
GPPL (GPIO_NV33_PG, 1, 20)
|
||||
|
||||
/* Ramp up NVVDD rail */
|
||||
\_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN)
|
||||
GPPL (GPIO_NVVDD_PG, 1, 5)
|
||||
|
||||
/* Ramp up PEXVDD rail */
|
||||
\_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN)
|
||||
GPPL (GPIO_PEXVDD_PG, 1, 5)
|
||||
|
||||
/* Ramp up FBVDD rail */
|
||||
\_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN)
|
||||
GPPL (GPIO_FBVDD_PG, 1, 5)
|
||||
|
||||
/* All rails are good */
|
||||
\_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG)
|
||||
Sleep (1)
|
||||
|
||||
/* Deassert PERST# */
|
||||
\_SB.PCI0.STXS (GPIO_GPU_PERST_L)
|
||||
}
|
||||
|
||||
/* GCOFF entry sequence */
|
||||
Method (PGOF, 0, Serialized)
|
||||
{
|
||||
/* Assert PERST# */
|
||||
\_SB.PCI0.CTXS (GPIO_GPU_PERST_L)
|
||||
Sleep (5)
|
||||
|
||||
/* All rails are about to go down */
|
||||
\_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG)
|
||||
|
||||
/* Ramp down FBVDD */
|
||||
\_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN)
|
||||
GPPL (GPIO_FBVDD_PG, 0, 20)
|
||||
|
||||
/* Ramp down PEXVDD */
|
||||
\_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN)
|
||||
GPPL (GPIO_PEXVDD_PG, 0, 20)
|
||||
|
||||
/* Ramp down NVVDD */
|
||||
\_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN)
|
||||
GPPL (GPIO_NVVDD_PG, 0, 20)
|
||||
|
||||
/* Ramp down NV33 */
|
||||
\_SB.PCI0.CTXS (GPIO_NV33_PWR_EN)
|
||||
GPPL (GPIO_NV33_PG, 0, 20)
|
||||
|
||||
/* Ramp down 1.8V */
|
||||
\_SB.PCI0.CTXS (GPIO_1V8_PWR_EN)
|
||||
GPPL (GPIO_1V8_PG, 0, 20)
|
||||
}
|
||||
|
||||
/* Handle deferred GC6 vs. poweron request */
|
||||
Method (NPON, 0, Serialized)
|
||||
{
|
||||
If (DFEN == GC6_DEFER_ENABLE) /* 1 */
|
||||
{
|
||||
If (DFCO == GC6_DEFER_TYPE_EXIT_GC6) /* 3 */
|
||||
{
|
||||
GC6O ()
|
||||
}
|
||||
|
||||
DFEN = GC6_DEFER_DISABLE
|
||||
}
|
||||
Else
|
||||
{
|
||||
PGON ()
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle deferred GC6 vs. poweroff request */
|
||||
Method (NPOF, 0, Serialized)
|
||||
{
|
||||
If (DFEN == GC6_DEFER_ENABLE)
|
||||
{
|
||||
/* Deferred GC6 entry */
|
||||
If (DFCI == NVJT_GPC_EGNS || DFCI == NVJT_GPC_EGIS)
|
||||
{
|
||||
GC6I ()
|
||||
}
|
||||
|
||||
DFEN = GC6_DEFER_DISABLE
|
||||
}
|
||||
Else
|
||||
{
|
||||
PGOF ()
|
||||
}
|
||||
}
|
||||
|
||||
Method (_ON, 0, Serialized)
|
||||
{
|
||||
PGON ()
|
||||
}
|
||||
|
||||
Method (_OFF, 0, Serialized)
|
||||
{
|
||||
PGOF ()
|
||||
}
|
||||
|
||||
/* Put device into D0 */
|
||||
Method (_PS0, 0, NotSerialized)
|
||||
{
|
||||
If (OPS0 == OPTIMUS_CONTROL_RUN_PS0)
|
||||
{
|
||||
/* Restore PCI config space */
|
||||
If (PCIO == PCI_OWNER_SBIOS)
|
||||
{
|
||||
VGAR = VGAB
|
||||
}
|
||||
|
||||
/* Poweron or deferred GC6 exit */
|
||||
NPON ()
|
||||
|
||||
OPS0 = OPTIMUS_CONTROL_NO_RUN_PS0
|
||||
}
|
||||
}
|
||||
|
||||
/* Put device into D3 */
|
||||
Method (_PS3, 0, NotSerialized)
|
||||
{
|
||||
If (OPCS == OPTIMUS_POWER_CONTROL_ENABLE)
|
||||
{
|
||||
/* Save PCI config space to ACPI buffer */
|
||||
If (PCIO == PCI_OWNER_SBIOS)
|
||||
{
|
||||
VGAB = VGAR
|
||||
}
|
||||
|
||||
/* Poweroff or deferred GC6 entry */
|
||||
NPOF ()
|
||||
|
||||
/* Because _PS3 ran _OFF, _PS0 must run _ON */
|
||||
OPS0 = OPTIMUS_CONTROL_RUN_PS0
|
||||
|
||||
/* OPCS is one-shot, so reset it */
|
||||
OPCS = OPTIMUS_POWER_CONTROL_DISABLE
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Normally, _ON and _OFF of the power resources listed in _PRx will be
|
||||
* evaluated before entering D0/D3. However, for Optimus, the package
|
||||
* should refer to the PCIe controller itself, not a dependent device.
|
||||
*/
|
||||
Name (_PR0, Package() { \_SB.PCI0.PEG0 })
|
||||
Name (_PR3, Package() { \_SB.PCI0.PEG0 })
|
||||
|
||||
Method (_STA, 0, Serialized)
|
||||
{
|
||||
If (GC6E == GC6_STATE_EXITED &&
|
||||
\_SB.PCI0.GTXS(GPIO_GPU_ALLRAILS_PG) == 1)
|
||||
{
|
||||
Return (0xF)
|
||||
}
|
||||
Else
|
||||
{
|
||||
Return (0)
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
/*
|
||||
* Poll a GPIO until it goes to the specified state
|
||||
* Arg0 == GPIO #
|
||||
* Arg1 == state (0 or 1)
|
||||
* Arg2 == timeout in ms
|
||||
*/
|
||||
Method (GPPL, 3, Serialized)
|
||||
{
|
||||
Local0 = GRXS (Arg0)
|
||||
Local7 = Arg2 * 10000
|
||||
Local7 = Timer + Local7
|
||||
While (Local0 != Arg1 && Timer < Local7)
|
||||
{
|
||||
Stall (10)
|
||||
Local0 = \_SB.PCI0.GRXS (Arg0)
|
||||
}
|
||||
}
|
||||
|
||||
/* Convert from 32-bit integer to 4-byte buffer (little-endian) */
|
||||
Method (ITOB, 1)
|
||||
{
|
||||
Local0 = Buffer(4) { 0, 0, 0, 0 }
|
||||
Local0[0] = Arg0 & 0xFF
|
||||
Local0[1] = (Arg0 >> 8) & 0xFF
|
||||
Local0[2] = (Arg0 >> 16) & 0xFF
|
||||
Local0[3] = (Arg0 >> 24) & 0xFF
|
||||
Return (Local0)
|
||||
}
|
||||
|
|
@ -44,4 +44,8 @@ DefinitionBlock(
|
|||
/* ACPI code for EC functions */
|
||||
#include <ec/google/chromeec/acpi/ec.asl>
|
||||
}
|
||||
|
||||
#if CONFIG(INCLUDE_NVIDIA_GPU_ASL)
|
||||
#include "acpi/gpu_top.asl"
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue