From c862e441627468cd8b27436a26b0153010f491c5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 14 Jun 2014 15:25:33 +0300 Subject: [PATCH] northbridge/intel: Drop use of set_top_of_ram() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We implement get_top_of_ram() on these chipset to resolve CBMEM location early in romstage. Call to set_top_ram() is not required. Change-Id: I492e436b0c32d2c24677265b35afd05f29dcd0f8 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/6031 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Vladimir Serbinenko Reviewed-by: Edward O'Callaghan --- src/northbridge/intel/gm45/northbridge.c | 2 -- src/northbridge/intel/i945/northbridge.c | 2 -- src/northbridge/intel/nehalem/northbridge.c | 2 -- src/northbridge/intel/sandybridge/northbridge.c | 2 -- 4 files changed, 8 deletions(-) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index afd270fecf..afac03589d 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -165,8 +165,6 @@ static void mch_domain_read_resources(device_t dev) fixed_mem_resource(dev, 7, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } - - set_top_of_ram(tomk << 10); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 948f5c13b7..68d6d912fd 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -170,8 +170,6 @@ static void pci_domain_set_resources(device_t dev) add_fixed_resources(dev, 7); assign_resources(dev->link_list); - - set_top_of_ram(tomk_stolen * 1024); } /* TODO We could determine how many PCIe busses we need in diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 639d24568b..071ff7f6a5 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -164,8 +164,6 @@ static void mc_read_resources(device_t dev) bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10); add_fixed_resources(dev, 10); - - set_top_of_ram(tseg_base); } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5f9912ff6d..b46ae2294d 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -251,8 +251,6 @@ static void pci_domain_set_resources(device_t dev) add_fixed_resources(dev, 6); assign_resources(dev->link_list); - - set_top_of_ram(tomk * 1024); } /* TODO We could determine how many PCIe busses we need in