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soc/amd/cezanne: populate some FSP-M UPDs 

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I81a812662f921d0bf8d436238d338b6a1fa6a9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2021-02-02 20:21:09 +01:00
parent 0589e3ce7f
commit c86acf4216
1 changed files with 11 additions and 0 deletions
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11
src/soc/amd/cezanne/romstage.c
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@ -3,11 +3,22 @@
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <arch/cpu.h> #include <arch/cpu.h>
#include <console/console.h> #include <console/console.h>
#include <console/uart.h>
#include <fsp/api.h> #include <fsp/api.h>
#include <program_loading.h> #include <program_loading.h>
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{ {
FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
mcfg->bert_size = CONFIG_ACPI_BERT_SIZE;
mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);
mcfg->serial_port_stride = CONFIG(DRIVERS_UART_8250MEM_32) ? 4 : 1;
mcfg->serial_port_baudrate = get_uart_baudrate();
mcfg->serial_port_refclk = uart_platform_refclk();
} }
asmlinkage void car_stage_entry(void) asmlinkage void car_stage_entry(void)