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Doc/psp_integration.md: Update infomation with latest document 

Update coreboot.org PSP Firmware Documentation with current internal
PSP documentation.

Signed-off-by: Altamshali Hirani <al.hirani@amd.corp-partner.google.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Change-Id: I677f86614b0fdc6377fb2e27932ed3a8ded27102
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Zheng Bao 2022-07-26 17:46:12 +08:00 committed by Felix Held
parent 05208b50c5
commit c86c0cdb11
1 changed files with 27 additions and 8 deletions
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35
Documentation/soc/amd/psp_integration.md
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@ -117,14 +117,23 @@ implementations currently use combo tables.
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Size | 0x04 | 32 | Size of PSP entry in bytes | | Size | 0x04 | 32 | Size of PSP entry in bytes |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Location / | 0x08 | 64 | Location: Physical Address | | Location / | 0x08 | 62 | Location: Physical Address |
| Value | | | of SPIROM location where | | Value | | | of SPIROM location where |
| | | | corresponding PSP entry | | | | | corresponding PSP entry |
| | | | located. | | | | | located. |
| | | | | | | | | |
| | | | Value: 64-bit value for the| | | | | Value: 62-bit value for the|
| | | | PSP Entry | | | | | PSP Entry |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Address Mode | 0x0F[7:6] | 2 | 00: x86 Physical address |
| | | | 01: offset from start of |
| | | | BIOS (flash offset) |
| | | | 02: offset from start of |
| | | | directory header |
| | | | 03: offset from start of |
| | | | partition |
+--------------+---------------+------------------+----------------------------+
``` ```
### PSP Directory Table Types ### PSP Directory Table Types
@ -172,6 +181,10 @@ implementations currently use combo tables.
* Intermediate Key Encryption Key, used to decrypt encrypted firmware images. * Intermediate Key Encryption Key, used to decrypt encrypted firmware images.
This is mandatory in order to support encrypted firmware. This is mandatory in order to support encrypted firmware.
**0x22**: PSP Token Unlock data
* Used to support time-bound Secure Debug unlock during boot. This entry may
be omitted if the Token Unlock debug feature is not required.
**0x24**: Security policy binary **0x24**: Security policy binary
* A security policy is applied to restrict the untrusted access to security * A security policy is applied to restrict the untrusted access to security
sensitive regions. sensitive regions.
@ -200,10 +213,6 @@ implementations currently use combo tables.
**0x52**: PSP boot loader usermode OEM application **0x52**: PSP boot loader usermode OEM application
* Supported only in certain SKUs. * Supported only in certain SKUs.
**0x22**: PSP Token Unlock data
* Used to support time-bound Secure Debug unlock during boot. This entry may
be omitted if the Token Unlock debug feature is not required.
### Firmware Version of Binaries ### Firmware Version of Binaries
Every firmware binary contains 256 bytes of a PSP Header, which includes Every firmware binary contains 256 bytes of a PSP Header, which includes
@ -302,15 +311,25 @@ The BIOS Directory table structure is slightly different from the PSP Directory:
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | | RomId | 0x03[4:3] | 2 | Which SPI device the |
| | | | content is placed in |
+--------------+---------------+------------------+----------------------------+
| Writeable | 0x03[5] | 1 | Region is writable or read |
| | | | only |
+--------------+---------------+------------------+----------------------------+
| Reserved | 0x03[7:6] | 2 | Reserved - Set to zero |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Size | 0x04 | 32 | Memory Region Size | | Size | 0x04 | 32 | Memory Region Size |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Source | 0x08 | 64 | Physical Address of SPIROM | | Source | 0x08 | 62 | Physical Address of SPIROM |
| Address | | | location where the data for| | Address | | | location where the data for|
| | | | the corresponding entry is | | | | | the corresponding entry is |
| | | | located | | | | | located |
+--------------+---------------+------------------+----------------------------+ +--------------+---------------+------------------+----------------------------+
| Entry Address| 0x0F[7:6] | 2 | Same as Entry Address Mode |
| Mode | | | in PSP directory table |
| | | | entry fields |
+--------------+---------------+------------------+----------------------------+
| Destination | 0x10 | 64 | Destination Address of | | Destination | 0x10 | 64 | Destination Address of |
| Address | | | memory location where the | | Address | | | memory location where the |
| | | | data for the corresponding | | | | | data for the corresponding |