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intel cache-as-ram: Move DCACHE_RAM_BASE 

Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.

As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.

There are no reasons to have this as board-specific setting.

Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-12-09 17:43:27 +02:00
parent c3e0389c05
commit c86c6b33e8
15 changed files with 20 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/intel/ep80579/Kconfig
View File

@ -14,7 +14,7 @@ if CPU_INTEL_EP80579
config DCACHE_RAM_BASE
hex
default 0xffaf8000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

2
src/cpu/intel/socket_441/Kconfig
View File

@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_BASE
hex
default 0xffaf8000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

2
src/cpu/intel/socket_BGA956/Kconfig
View File

@ -8,7 +8,7 @@ if CPU_INTEL_SOCKET_BGA956
config DCACHE_RAM_BASE
hex
default 0xffaf8000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

2
src/cpu/intel/socket_FCBGA559/Kconfig
View File

@ -11,7 +11,7 @@ config SOCKET_SPECIFIC_OPTIONS
config DCACHE_RAM_BASE
hex
default 0xffafc000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

12
src/cpu/intel/socket_LGA771/Kconfig
View File

@ -4,3 +4,15 @@ config CPU_INTEL_SOCKET_LGA771
select SSE2
select MMX
select AP_IN_SIPI_WAIT
if CPU_INTEL_SOCKET_LGA771
config DCACHE_RAM_BASE
hex
default 0xfefc0000
config DCACHE_RAM_SIZE
hex
default 0x8000
endif

2
src/cpu/intel/socket_mFCPGA478/Kconfig
View File

@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
config DCACHE_RAM_BASE
hex
default 0xffaf8000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

2
src/cpu/intel/socket_mPGA478MN/Kconfig
View File

@ -9,7 +9,7 @@ if CPU_INTEL_SOCKET_MPGA478MN
config DCACHE_RAM_BASE
hex
default 0xffaf8000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

2
src/cpu/intel/socket_mPGA604/Kconfig
View File

@ -22,7 +22,7 @@ config SSE2
config DCACHE_RAM_BASE
hex
default 0x0ffafc000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex

8
src/mainboard/apple/macbook21/Kconfig
View File

@ -27,14 +27,6 @@ config MAINBOARD_DIR
string
default apple/macbook21
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
if BOARD_APPLE_MACBOOK21
config MAINBOARD_PART_NUMBER

8
src/mainboard/asus/dsbf/Kconfig
View File

@ -15,14 +15,6 @@ config MAINBOARD_DIR
string
default asus/dsbf
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
config MAINBOARD_PART_NUMBER
string
default "DSBF"

8
src/mainboard/ibase/mb899/Kconfig
View File

@ -21,14 +21,6 @@ config MAINBOARD_DIR
string
default ibase/mb899
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
config MAINBOARD_PART_NUMBER
string
default "MB899"

8
src/mainboard/lenovo/t60/Kconfig
View File

@ -30,14 +30,6 @@ config MAINBOARD_DIR
string
default lenovo/t60
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
config MAINBOARD_PART_NUMBER
string
default "ThinkPad T60"

8
src/mainboard/lenovo/x60/Kconfig
View File

@ -33,14 +33,6 @@ config MAINBOARD_DIR
string
default lenovo/x60
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
config MAINBOARD_PART_NUMBER
string
default "ThinkPad X60"

8
src/mainboard/supermicro/x7db8/Kconfig
View File

@ -15,14 +15,6 @@ config MAINBOARD_DIR
string
default supermicro/x7db8
config DCACHE_RAM_BASE
hex
default 0xffdf8000
config DCACHE_RAM_SIZE
hex
default 0x8000
config MAINBOARD_PART_NUMBER
string
default "X7DB8 / X7DB8+"

2
src/northbridge/intel/nehalem/Kconfig
View File

@ -39,7 +39,7 @@ config VGA_BIOS_ID
config DCACHE_RAM_BASE
hex
default 0xff7f0000
default 0xfefc0000
config DCACHE_RAM_SIZE
hex