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soc/amd/picasso/include/iomap: add comment about ACPI IO assignment 

Finally figured out why ACPI_GPE0_BLK only being 4 bytes after
ACPI_CPU_CONTROL won't work and its due to the CPU trapping 8 IO
addresses from ACPI_CPU_CONTROL on for C state control. This is set up
in set_cstate_io_addr by writing the ACPI_CPU_CONTROL value into
MSR_CSTATE_ADDRESS.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iedf53bbdae6ca65224601aad5cd1163df4b54131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-03-03 18:40:14 +01:00
parent f773e12795
commit c8755141c0
1 changed files with 2 additions and 2 deletions
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4
src/soc/amd/picasso/include/soc/iomap.h
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@ -69,8 +69,8 @@
#define ACPI_PM1_EN (ACPI_PM_EVT_BLK + 0x02) /* 2 bytes */
#define ACPI_PM1_CNT_BLK (ACPI_IO_BASE + 0x04) /* 2 bytes */
#define ACPI_PM_TMR_BLK (ACPI_IO_BASE + 0x08) /* 4 bytes */
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10)
/* doc says 0x14 for GPE0_BLK but FT5 only works with 0x20 */
#define ACPI_CPU_CONTROL (ACPI_IO_BASE + 0x10) /* 8 bytes */
/* doc says 0x14 for GPE0_BLK but 8 bytes from ACPI_CPU_CONTROL on are trapped in CPU core */
#define ACPI_GPE0_BLK (ACPI_IO_BASE + 0x20) /* 8 bytes */
#define ACPI_GPE0_STS (ACPI_GPE0_BLK + 0x00) /* 4 bytes */
#define ACPI_GPE0_EN (ACPI_GPE0_BLK + 0x04) /* 4 bytes */