diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index f47ba5f05e..fffe3f80b4 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -15,7 +16,7 @@ _cache_as_ram_setup: bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -28,7 +29,7 @@ wait_for_sipi: bt $12, %eax jc wait_for_sipi - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -57,7 +58,7 @@ clear_var_mtrr: dec %ebx jnz clear_var_mtrr - post_code(0x22) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr @@ -82,7 +83,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl $_car_mtrr_start, %eax @@ -90,7 +91,7 @@ addrsize_set_high: xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -98,7 +99,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -126,7 +127,7 @@ addrsize_set_high: shr $2, %ecx rep stosl - post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -145,7 +146,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -179,7 +180,7 @@ addrsize_set_high: #endif before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 0451bb4dd5..2ac660c9aa 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -20,7 +21,7 @@ bootblock_pre_c_entry: jmp check_mtrr /* Check if CPU properly reset */ cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Send INIT IPI to all excluding ourself. */ movl $0x000C4500, %eax @@ -33,14 +34,14 @@ wait_for_sipi: bt $12, %eax jc wait_for_sipi - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Clean-up MTRR_DEF_TYPE_MSR. */ movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr - post_code(0x22) + post_code(POST_SOC_CLEAR_FIXED_MTRRS) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx xor %eax, %eax @@ -86,7 +87,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x23) + post_code(POST_SOC_SET_MTRR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx movl car_mtrr_start, %eax @@ -94,7 +95,7 @@ addrsize_set_high: xorl %edx, %edx wrmsr - post_code(0x24) + post_code(POST_SOC_SET_MTRR_MASK) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr @@ -115,7 +116,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x25) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -186,7 +187,7 @@ end_microcode_update: orl $3, %eax wrmsr - post_code(0x26) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -197,7 +198,7 @@ end_microcode_update: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x28) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -232,7 +233,7 @@ end_microcode_update: #endif before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 2834e76090..56370f8841 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -12,14 +13,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -35,7 +36,7 @@ chipset_teardown_car: andl $~1, %eax wrmsr - post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 887bb22477..c19fa3cf6c 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -13,7 +14,7 @@ _cache_as_ram_setup: bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) /* Clear/disable fixed MTRRs */ mov $fixed_mtrr_list_size, %ebx @@ -41,7 +42,7 @@ clear_var_mtrr: inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -49,7 +50,7 @@ clear_var_mtrr: andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax @@ -67,7 +68,7 @@ addrsize_set_high: movl $MTRR_PHYS_MASK(1), %ecx wrmsr - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -83,7 +84,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -91,7 +92,7 @@ addrsize_set_high: orl $MTRR_DEF_TYPE_EN, %eax wrmsr - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ movl %cr0, %eax @@ -113,7 +114,7 @@ addrsize_set_high: xorl %eax, %eax rep stosl - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Enable Cache-as-RAM mode by disabling cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -132,7 +133,7 @@ addrsize_set_high: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -155,7 +156,7 @@ addrsize_set_high: pushl %eax /* tsc[31:0] */ before_c_entry: - post_code(0x29) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 9ac9e22c3e..01abdf884f 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -19,7 +20,7 @@ _cache_as_ram_setup: bootblock_pre_c_entry: cache_as_ram: - post_code(0x20) + post_code(POST_BOOTBLOCK_CAR) movl $LAPIC_BASE_MSR, %ecx rdmsr @@ -52,7 +53,7 @@ clear_var_mtrr: inc %ecx dec %ebx jnz clear_var_mtrr - post_code(0x21) + post_code(POST_SOC_SET_DEF_MTRR_TYPE) /* Configure the default memory type to uncacheable. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -60,7 +61,7 @@ clear_var_mtrr: andl $(~0x00000cff), %eax wrmsr - post_code(0x22) + post_code(POST_SOC_DETERMINE_CPU_ADDR_BITS) /* Determine CPU_ADDR_BITS and load PHYSMASK high * word to %edx. @@ -104,7 +105,7 @@ addrsize_set_high: bsp_init: - post_code(0x23) + post_code(POST_SOC_BSP_INIT) /* Send INIT IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -118,7 +119,7 @@ bsp_init: andl $LAPIC_ICR_BUSY, %ecx jnz 1b - post_code(0x24) + post_code(POST_SOC_COUNT_CORES) movl $1, %eax cpuid @@ -153,7 +154,7 @@ cores_counted: hyper_threading_cpu: - post_code(0x25) + post_code(POST_SOC_CPU_HYPER_THREADING) /* Send Start IPI to all excluding ourself. */ movl LAPIC(ICR), %edi @@ -168,7 +169,7 @@ hyper_threading_cpu: andl $LAPIC_ICR_BUSY, %ecx jnz 1b - post_code(0x26) + post_code(POST_SOC_CPU_SIBLING_DELAY) /* Wait for sibling CPU to start. */ 1: movl $(MTRR_PHYS_BASE(0)), %ecx @@ -184,14 +185,14 @@ hyper_threading_cpu: ap_init: - post_code(0x27) + post_code(POST_SOC_CPU_AP_INIT) /* Do not disable cache (so BSP can enable it). */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 - post_code(0x28) + post_code(POST_SOC_SET_MTRR_BASE) /* MTRR registers are shared between HT siblings. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -199,7 +200,7 @@ ap_init: xorl %edx, %edx wrmsr - post_code(0x29) + post_code(POST_SOC_AP_HALT) ap_halt: cli @@ -210,7 +211,7 @@ ap_halt: sipi_complete: - post_code(0x2a) + post_code(POST_SOC_SET_CAR_BASE) /* Set Cache-as-RAM base address. */ movl $(MTRR_PHYS_BASE(0)), %ecx @@ -226,7 +227,7 @@ sipi_complete: orl $MTRR_PHYS_MASK_VALID, %eax wrmsr - post_code(0x2b) + post_code(POST_SOC_ENABLE_MTRRS) /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -269,7 +270,7 @@ has_msr_11e: wrmsr no_msr_11e: - post_code(0x2c) + post_code(POST_SOC_ENABLE_CACHE) /* Cache the whole rom to fetch microcode updates */ movl $MTRR_PHYS_BASE(1), %ecx @@ -296,7 +297,7 @@ no_msr_11e: jmp update_bsp_microcode end_microcode_update: #endif - post_code(0x2d) + post_code(POST_SOC_DISABLE_CACHE) /* Disable caching to change MTRR's. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -336,7 +337,7 @@ cache_rom: wrmsr fill_cache: - post_code(0x2e) + post_code(POST_SOC_FILL_CACHE) /* Enable cache. */ movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax @@ -379,7 +380,7 @@ fill_cache: #endif before_c_entry: - post_code(0x2f) + post_code(POST_BOOTBLOCK_BEFORE_C_ENTRY) call bootblock_c_entry_bist /* Should never see this postcode */ diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 108342ff3c..1684407e81 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -10,14 +11,14 @@ chipset_teardown_car: pop %esp - post_code(0x30) + post_code(POST_POSTCAR_DISABLE_CACHE) /* Disable cache. */ movl %cr0, %eax orl $CR0_CacheDisable, %eax movl %eax, %cr0 - post_code(0x31) + post_code(POST_POSTCAR_DISABLE_DEF_MTRR) /* Disable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx @@ -25,7 +26,7 @@ chipset_teardown_car: andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr - post_code(0x32) + post_code(POST_POSTCAR_TEARDOWN_DONE) /* Return to caller. */ jmp *%esp diff --git a/src/include/cpu/intel/post_codes.h b/src/include/cpu/intel/post_codes.h new file mode 100644 index 0000000000..3db0aeb939 --- /dev/null +++ b/src/include/cpu/intel/post_codes.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CPU_INTEL_CAR_POST_CODES_H +#define CPU_INTEL_CAR_POST_CODES_H + +#define POST_BOOTBLOCK_CAR 0x20 +#define POST_SOC_SET_DEF_MTRR_TYPE 0x21 +#define POST_SOC_CLEAR_FIXED_MTRRS 0x22 // Intentional Duplicate +#define POST_SOC_DETERMINE_CPU_ADDR_BITS 0x22 +#define POST_SOC_BSP_INIT 0x23 +#define POST_SOC_COUNT_CORES 0x24 +#define POST_SOC_CPU_HYPER_THREADING 0x25 +#define POST_SOC_CPU_SIBLING_DELAY 0x26 +#define POST_SOC_CPU_AP_INIT 0x27 +#define POST_SOC_SET_MTRR_BASE 0x28 +#define POST_SOC_SET_MTRR_MASK 0x29 // Intentional Duplicate +#define POST_SOC_AP_HALT 0x29 +#define POST_SOC_SET_CAR_BASE 0x2a +#define POST_SOC_ENABLE_MTRRS 0x2b +#define POST_SOC_ENABLE_CACHE 0x2c +#define POST_SOC_DISABLE_CACHE 0x2d +#define POST_SOC_FILL_CACHE 0x2e +#define POST_BOOTBLOCK_BEFORE_C_ENTRY 0x2f + +#define POST_POSTCAR_DISABLE_CACHE 0x30 +#define POST_POSTCAR_DISABLE_DEF_MTRR 0x31 +#define POST_POSTCAR_TEARDOWN_DONE 0x32 + +#endif