diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index 3d60b28009..8e2f9edb01 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -110,363 +110,6 @@ void clock_select_i2s_clk_source(void);
  */
 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
 
-struct exynos5_clock {
-	uint32_t	apll_lock;		/* base + 0 */
-	uint8_t		res1[0xfc];
-	uint32_t	apll_con0;
-	uint32_t	apll_con1;
-	uint8_t		res2[0xf8];
-	uint32_t	src_cpu;
-	uint8_t		res3[0x1fc];
-	uint32_t	mux_stat_cpu;
-	uint8_t		res4[0xfc];
-	uint32_t	div_cpu0;
-	uint32_t	div_cpu1;
-	uint8_t		res5[0xf8];
-	uint32_t	div_stat_cpu0;
-	uint32_t	div_stat_cpu1;
-	uint8_t		res6[0x1f8];
-	uint32_t	gate_sclk_cpu;
-	uint8_t		res7[0x1fc];
-	uint32_t	clkout_cmu_cpu;
-	uint32_t	clkout_cmu_cpu_div_stat;
-	uint8_t		res8[0x5f8];
-
-	uint32_t	armclk_stopctrl;	/* base + 0x1000 */
-	uint32_t	atclk_stopctrl;
-	uint8_t		res9[0x8];
-	uint32_t	parityfail_status;
-	uint32_t	parityfail_clear;
-	uint8_t		res10[0x8];
-	uint32_t	pwr_ctrl;
-	uint32_t	pwr_ctr2;
-	uint8_t		res11[0xd8];
-	uint32_t	apll_con0_l8;
-	uint32_t	apll_con0_l7;
-	uint32_t	apll_con0_l6;
-	uint32_t	apll_con0_l5;
-	uint32_t	apll_con0_l4;
-	uint32_t	apll_con0_l3;
-	uint32_t	apll_con0_l2;
-	uint32_t	apll_con0_l1;
-	uint32_t	iem_control;
-	uint8_t		res12[0xdc];
-	uint32_t	apll_con1_l8;
-	uint32_t	apll_con1_l7;
-	uint32_t	apll_con1_l6;
-	uint32_t	apll_con1_l5;
-	uint32_t	apll_con1_l4;
-	uint32_t	apll_con1_l3;
-	uint32_t	apll_con1_l2;
-	uint32_t	apll_con1_l1;
-	uint8_t		res13[0xe0];
-	uint32_t	div_iem_l8;
-	uint32_t	div_iem_l7;
-	uint32_t	div_iem_l6;
-	uint32_t	div_iem_l5;
-	uint32_t	div_iem_l4;
-	uint32_t	div_iem_l3;
-	uint32_t	div_iem_l2;
-	uint32_t	div_iem_l1;
-	uint8_t		res14[0x2ce0];
-
-	uint32_t	mpll_lock;		/* base + 0x4000 */
-	uint8_t		res15[0xfc];
-	uint32_t	mpll_con0;
-	uint32_t	mpll_con1;
-	uint8_t		res16[0xf8];
-	uint32_t	src_core0;
-	uint32_t	src_core1;
-	uint8_t		res17[0xf8];
-	uint32_t	src_mask_core;
-	uint8_t		res18[0x100];
-	uint32_t	mux_stat_core1;
-	uint8_t		res19[0xf8];
-	uint32_t	div_core0;
-	uint32_t	div_core1;
-	uint32_t	div_sysrgt;
-	uint8_t		res20[0xf4];
-	uint32_t	div_stat_core0;
-	uint32_t	div_stat_core1;
-	uint32_t	div_stat_sysrgt;
-	uint8_t		res21[0x2f4];
-	uint32_t	gate_ip_core;
-	uint32_t	gate_ip_sysrgt;
-	uint8_t		res22[0xf8];
-	uint32_t	clkout_cmu_core;
-	uint32_t	clkout_cmu_core_div_stat;
-	uint8_t		res23[0x5f8];
-
-	uint32_t	dcgidx_map0;		/* base + 0x5000 */
-	uint32_t	dcgidx_map1;
-	uint32_t	dcgidx_map2;
-	uint8_t		res24[0x14];
-	uint32_t	dcgperf_map0;
-	uint32_t	dcgperf_map1;
-	uint8_t		res25[0x18];
-	uint32_t	dvcidx_map;
-	uint8_t		res26[0x1c];
-	uint32_t	freq_cpu;
-	uint32_t	freq_dpm;
-	uint8_t		res27[0x18];
-	uint32_t	dvsemclk_en;
-	uint32_t	maxperf;
-	uint8_t		res28[0x3478];
-
-	uint32_t	div_acp;		/* base + 0x8500 */
-	uint8_t		res29[0xfc];
-	uint32_t	div_stat_acp;
-	uint8_t		res30[0x1fc];
-	uint32_t	gate_ip_acp;
-	uint8_t		res31a[0xfc];
-	uint32_t	div_syslft;
-	uint8_t		res31b[0xc];
-	uint32_t	div_stat_syslft;
-	uint8_t		res31c[0xc];
-	uint32_t	gate_bus_syslft;
-	uint8_t		res31d[0xdc];
-	uint32_t	clkout_cmu_acp;
-	uint32_t	clkout_cmu_acp_div_stat;
-	uint8_t		res32[0x38f8];
-
-	uint32_t	div_isp0;		/* base + 0xc300 */
-	uint32_t	div_isp1;
-	uint32_t	div_isp2;
-	uint8_t		res33[0xf4];
-
-	uint32_t	div_stat_isp0;		/* base + 0xc400 */
-	uint32_t	div_stat_isp1;
-	uint32_t	div_stat_isp2;
-	uint8_t		res34[0x3f4];
-
-	uint32_t	gate_ip_isp0;		/* base + 0xc800 */
-	uint32_t	gate_ip_isp1;
-	uint8_t		res35[0xf8];
-	uint32_t	gate_sclk_isp;
-	uint8_t		res36[0xc];
-	uint32_t	mcuisp_pwr_ctrl;
-	uint8_t		res37[0xec];
-	uint32_t	clkout_cmu_isp;
-	uint32_t	clkout_cmu_isp_div_stat;
-	uint8_t		res38[0x3618];
-
-	uint32_t	cpll_lock;		/* base + 0x10020 */
-	uint8_t		res39[0xc];
-	uint32_t	epll_lock;
-	uint8_t		res40[0xc];
-	uint32_t	vpll_lock;
-	uint8_t		res41a[0xc];
-	uint32_t	gpll_lock;
-	uint8_t		res41b[0xcc];
-	uint32_t	cpll_con0;
-	uint32_t	cpll_con1;
-	uint8_t		res42[0x8];
-	uint32_t	epll_con0;
-	uint32_t	epll_con1;
-	uint32_t	epll_con2;
-	uint8_t		res43[0x4];
-	uint32_t	vpll_con0;
-	uint32_t	vpll_con1;
-	uint32_t	vpll_con2;
-	uint8_t		res44a[0x4];
-	uint32_t	gpll_con0;
-	uint32_t	gpll_con1;
-	uint8_t		res44b[0xb8];
-	uint32_t	src_top0;
-	uint32_t	src_top1;
-	uint32_t	src_top2;
-	uint32_t	src_top3;
-	uint32_t	src_gscl;
-	uint32_t	src_disp0_0;
-	uint32_t	src_disp0_1;
-	uint32_t	src_disp1_0;
-	uint32_t	src_disp1_1;
-	uint8_t		res46[0xc];
-	uint32_t	src_mau;
-	uint32_t	src_fsys;
-	uint8_t		res47[0x8];
-	uint32_t	src_peric0;
-	uint32_t	src_peric1;
-	uint8_t		res48[0x18];
-	uint32_t	sclk_src_isp;
-	uint8_t		res49[0x9c];
-	uint32_t	src_mask_top;
-	uint8_t		res50[0xc];
-	uint32_t	src_mask_gscl;
-	uint32_t	src_mask_disp0_0;
-	uint32_t	src_mask_disp0_1;
-	uint32_t	src_mask_disp1_0;
-	uint32_t	src_mask_disp1_1;
-	uint32_t	src_mask_maudio;
-	uint8_t		res52[0x8];
-	uint32_t	src_mask_fsys;
-	uint8_t		res53[0xc];
-	uint32_t	src_mask_peric0;
-	uint32_t	src_mask_peric1;
-	uint8_t		res54[0x18];
-	uint32_t	src_mask_isp;
-	uint8_t		res55[0x9c];
-	uint32_t	mux_stat_top0;
-	uint32_t	mux_stat_top1;
-	uint32_t	mux_stat_top2;
-	uint32_t	mux_stat_top3;
-	uint8_t		res56[0xf0];
-	uint32_t	div_top0;
-	uint32_t	div_top1;
-	uint8_t		res57[0x8];
-	uint32_t	div_gscl;
-	uint32_t	div_disp0_0;
-	uint32_t	div_disp0_1;
-	uint32_t	div_disp1_0;
-	uint32_t	div_disp1_1;
-	uint8_t		res59[0x8];
-	uint32_t	div_gen;
-	uint8_t		res60[0x4];
-	uint32_t	div_mau;
-	uint32_t	div_fsys0;
-	uint32_t	div_fsys1;
-	uint32_t	div_fsys2;
-	uint32_t	div_fsys3;
-	uint32_t	div_peric0;
-	uint32_t	div_peric1;
-	uint32_t	div_peric2;
-	uint32_t	div_peric3;
-	uint32_t	div_peric4;
-	uint32_t	div_peric5;
-	uint8_t		res61[0x10];
-	uint32_t	sclk_div_isp;
-	uint8_t		res62[0xc];
-	uint32_t	div2_ratio0;
-	uint32_t	div2_ratio1;
-	uint8_t		res63[0x8];
-	uint32_t	div4_ratio;
-	uint8_t		res64[0x6c];
-	uint32_t	div_stat_top0;
-	uint32_t	div_stat_top1;
-	uint8_t		res65[0x8];
-	uint32_t	div_stat_gscl;
-	uint32_t	div_stat_disp0_0;
-	uint32_t	div_stat_disp0_1;
-	uint32_t	div_stat_disp1_0;
-	uint32_t	div_stat_disp1_1;
-	uint8_t		res67[0x8];
-	uint32_t	div_stat_gen;
-	uint8_t		res68[0x4];
-	uint32_t	div_stat_maudio;
-	uint32_t	div_stat_fsys0;
-	uint32_t	div_stat_fsys1;
-	uint32_t	div_stat_fsys2;
-	uint32_t	div_stat_fsys3;
-	uint32_t	div_stat_peric0;
-	uint32_t	div_stat_peric1;
-	uint32_t	div_stat_peric2;
-	uint32_t	div_stat_peric3;
-	uint32_t	div_stat_peric4;
-	uint32_t	div_stat_peric5;
-	uint8_t		res69[0x10];
-	uint32_t	sclk_div_stat_isp;
-	uint8_t		res70[0xc];
-	uint32_t	div2_stat0;
-	uint32_t	div2_stat1;
-	uint8_t		res71[0x8];
-	uint32_t	div4_stat;
-	uint8_t		res72[0x180];
-	uint32_t	gate_top_sclk_disp0;
-	uint32_t	gate_top_sclk_disp1;
-	uint32_t	gate_top_sclk_gen;
-	uint8_t		res74[0xc];
-	uint32_t	gate_top_sclk_mau;
-	uint32_t	gate_top_sclk_fsys;
-	uint8_t		res75[0xc];
-	uint32_t	gate_top_sclk_peric;
-	uint8_t		res76[0x1c];
-	uint32_t	gate_top_sclk_isp;
-	uint8_t		res77[0xac];
-	uint32_t	gate_ip_gscl;
-	uint32_t	gate_ip_disp0;
-	uint32_t	gate_ip_disp1;
-	uint32_t	gate_ip_mfc;
-	uint32_t	gate_ip_g3d;
-	uint32_t	gate_ip_gen;
-	uint8_t		res79[0xc];
-	uint32_t	gate_ip_fsys;
-	uint8_t		res80[0x4];
-	uint32_t	gate_ip_gps;
-	uint32_t	gate_ip_peric;
-	uint8_t		res81[0xc];
-	uint32_t	gate_ip_peris;
-	uint8_t		res82[0x1c];
-	uint32_t	gate_block;
-	uint8_t		res83[0x7c];
-	uint32_t	clkout_cmu_top;
-	uint32_t	clkout_cmu_top_div_stat;
-	uint8_t		res84[0x37f8];
-
-	uint32_t	src_lex;		/* base + 0x14200 */
-	uint8_t		res85[0x1fc];
-	uint32_t	mux_stat_lex;
-	uint8_t		res85b[0xfc];
-	uint32_t	div_lex;
-	uint8_t		res86[0xfc];
-	uint32_t	div_stat_lex;
-	uint8_t		res87[0x1fc];
-	uint32_t	gate_ip_lex;
-	uint8_t		res88[0x1fc];
-	uint32_t	clkout_cmu_lex;
-	uint32_t	clkout_cmu_lex_div_stat;
-	uint8_t		res89[0x3af8];
-
-	uint32_t	div_r0x;		/* base + 0x18500 */
-	uint8_t		res90[0xfc];
-	uint32_t	div_stat_r0x;
-	uint8_t		res91[0x1fc];
-	uint32_t	gate_ip_r0x;
-	uint8_t		res92[0x1fc];
-	uint32_t	clkout_cmu_r0x;
-	uint32_t	clkout_cmu_r0x_div_stat;
-	uint8_t		res94[0x3af8];
-
-	uint32_t	div_r1x;		/* base + 0x1c500 */
-	uint8_t		res95[0xfc];
-	uint32_t	div_stat_r1x;
-	uint8_t		res96[0x1fc];
-	uint32_t	gate_ip_r1x;
-	uint8_t		res97[0x1fc];
-	uint32_t	clkout_cmu_r1x;
-	uint32_t	clkout_cmu_r1x_div_stat;
-	uint8_t		res98[0x3608];
-
-	uint32_t	bpll_lock;		/* base + 0x2000c */
-	uint8_t		res99[0xfc];
-	uint32_t	bpll_con0;
-	uint32_t	bpll_con1;
-	uint8_t		res100[0xe8];
-	uint32_t	src_cdrex;
-	uint8_t		res101[0x1fc];
-	uint32_t	mux_stat_cdrex;
-	uint8_t		res102[0xfc];
-	uint32_t	div_cdrex;
-	uint32_t	div_cdrex2;
-	uint8_t		res103[0xf8];
-	uint32_t	div_stat_cdrex;
-	uint8_t		res104[0x2fc];
-	uint32_t	gate_ip_cdrex;
-	uint8_t		res105[0xc];
-	uint32_t	c2c_monitor;
-	uint32_t	dmc_pwr_ctrl;
-	uint8_t		res106[0x4];
-	uint32_t	drex2_pause;
-	uint8_t		res107[0xe0];
-	uint32_t	clkout_cmu_cdrex;
-	uint32_t	clkout_cmu_cdrex_div_stat;
-	uint8_t		res108[0x8];
-	uint32_t	lpddr3phy_ctrl;
-	uint8_t		res109a[0xc];
-	uint32_t	lpddr3phy_con3;
-	uint32_t	pll_div2_sel;
-	uint8_t		res109b[0xf5e4];
-};
-
 struct exynos5420_clock {
 	uint32_t	apll_lock;		/* 0x10010000 */
 	uint8_t		res1[0xfc];
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index 8799149627..e5ab001374 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -69,8 +69,7 @@ static struct st_epll_con_val epll_div[] = {
 /* exynos5: return pll clock frequency */
 unsigned long get_pll_clk(int pllreg)
 {
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
 	unsigned int freq;
 
@@ -146,44 +145,44 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 	struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
 	unsigned long sclk, sub_clk;
 	unsigned int src, div, sub_div;
-	struct exynos5_clock *clk = samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
 	case PERIPH_ID_UART1:
 	case PERIPH_ID_UART2:
 	case PERIPH_ID_UART3:
-		src = readl(&clk->src_peric0);
-		div = readl(&clk->div_peric0);
+		src = readl(&clk->clk_src_peric0);
+		div = readl(&clk->clk_div_peric0);
 		break;
 	case PERIPH_ID_PWM0:
 	case PERIPH_ID_PWM1:
 	case PERIPH_ID_PWM2:
 	case PERIPH_ID_PWM3:
 	case PERIPH_ID_PWM4:
-		src = readl(&clk->src_peric0);
-		div = readl(&clk->div_peric3);
+		src = readl(&clk->clk_src_peric0);
+		div = readl(&clk->clk_div_peric3);
 		break;
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
-		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric1);
+		src = readl(&clk->clk_src_peric1);
+		div = readl(&clk->clk_div_peric1);
 		break;
 	case PERIPH_ID_SPI2:
-		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric2);
+		src = readl(&clk->clk_src_peric1);
+		div = readl(&clk->clk_div_peric2);
 		break;
 	case PERIPH_ID_SPI3:
 	case PERIPH_ID_SPI4:
-		src = readl(&clk->sclk_src_isp);
-		div = readl(&clk->sclk_div_isp);
+		src = readl(&clk->clk_src_isp);
+		div = readl(&clk->clk_div_isp1);
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC2:
 	case PERIPH_ID_SDMMC3:
-		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys1);
+		src = readl(&clk->clk_src_fsys);
+		div = readl(&clk->clk_div_fsys1);
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -197,8 +196,8 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 	case PERIPH_ID_I2C9:
 	case PERIPH_ID_I2C10:
 		sclk = get_pll_clk(MPLL);
-		sub_div = ((readl(&clk->div_top1) >> 24) & 0x7) + 1;
-		div = (readl(&clk->div_top0) & 0x7) + 1;
+		sub_div = ((readl(&clk->clk_div_top1) >> 24) & 0x7) + 1;
+		div = (readl(&clk->clk_div_top0) & 0x7) + 1;
 		return (sclk / sub_div) / div;
 	default:
 		printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
@@ -234,13 +233,13 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 /* exynos5: return ARM clock frequency */
 unsigned long get_arm_clk(void)
 {
-	struct exynos5_clock *clk = samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned long div;
 	unsigned long armclk;
 	unsigned int arm_ratio;
 	unsigned int arm2_ratio;
 
-	div = readl(&clk->div_cpu0);
+	div = readl(&clk->clk_div_cpu0);
 
 	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 	arm_ratio = (div >> 0) & 0x7;
@@ -255,8 +254,7 @@ unsigned long get_arm_clk(void)
 /* exynos5: set the mmc clock */
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	void *addr;
 	unsigned int val, shift;
 
@@ -271,8 +269,7 @@ void set_mmc_clk(int dev_index, unsigned int div)
 
 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned shift;
 	unsigned mask = 0xff;
 	u32 *reg;
@@ -287,24 +284,24 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 	 */
 	switch (periph_id) {
 	case PERIPH_ID_SPI0:
-		reg = &clk->div_peric1;
+		reg = &clk->clk_div_peric4;
 		shift = 8;
 		break;
 	case PERIPH_ID_SPI1:
-		reg = &clk->div_peric1;
-		shift = 24;
+		reg = &clk->clk_div_peric4;
+		shift = 16;
 		break;
 	case PERIPH_ID_SPI2:
-		reg = &clk->div_peric2;
-		shift = 8;
+		reg = &clk->clk_div_peric4;
+		shift = 24;
 		break;
 	case PERIPH_ID_SPI3:
-		reg = &clk->sclk_div_isp;
-		shift = 4;
+		reg = &clk->clk_div_isp1;
+		shift = 0;
 		break;
 	case PERIPH_ID_SPI4:
-		reg = &clk->sclk_div_isp;
-		shift = 16;
+		reg = &clk->clk_div_isp1;
+		shift = 8;
 		break;
 	default:
 		printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
@@ -316,32 +313,31 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 
 void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned shift;
 	unsigned mask = 0xff;
 	u32 *reg;
 
 	switch (periph_id) {
 	case PERIPH_ID_SPI0:
-		reg = &clk->div_peric1;
-		shift = 0;
+		reg = &clk->clk_div_peric1;
+		shift = 20;
 		break;
 	case PERIPH_ID_SPI1:
-		reg = &clk->div_peric1;
-		shift = 16;
+		reg = &clk->clk_div_peric1;
+		shift = 24;
 		break;
 	case PERIPH_ID_SPI2:
-		reg = &clk->div_peric2;
-		shift = 0;
+		reg = &clk->clk_div_peric1;
+		shift = 28;
 		break;
 	case PERIPH_ID_SPI3:
-		reg = &clk->sclk_div_isp;
-		shift = 0;
+		reg = &clk->clk_div_isp1;
+		shift = 16;
 		break;
 	case PERIPH_ID_SPI4:
-		reg = &clk->sclk_div_isp;
-		shift = 12;
+		reg = &clk->clk_div_isp1;
+		shift = 20;
 		break;
 	default:
 		printk(BIOS_DEBUG, "%s: Unsupported peripheral ID %d\n", __func__,
@@ -441,8 +437,7 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate)
 
 int clock_set_mshci(enum periph_id peripheral)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	u32 *addr;
 	unsigned int clock;
 	unsigned int tmp;
@@ -459,10 +454,10 @@ int clock_set_mshci(enum periph_id peripheral)
 	 */
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		addr = &clk->div_fsys1;
+		addr = &clk->clk_div_fsys1;
 		break;
 	case PERIPH_ID_SDMMC2:
-		addr = &clk->div_fsys2;
+		addr = &clk->clk_div_fsys2;
 		break;
 	default:
 		printk(BIOS_DEBUG, "invalid peripheral\n");
@@ -484,8 +479,7 @@ int clock_epll_set_rate(unsigned long rate)
 	unsigned int i;
 	unsigned int lockcnt;
 	unsigned int start;
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 
 	epll_con = readl(&clk->epll_con0);
 	epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
@@ -534,17 +528,15 @@ int clock_epll_set_rate(unsigned long rate)
 
 void clock_select_i2s_clk_source(void)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 
-	clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+	clrsetbits_le32(&clk->clk_src_peric1, AUDIO1_SEL_MASK,
 			(CLK_SRC_SCLK_EPLL));
 }
 
 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
+	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned int div ;
 
 	if ((dst_frq == 0) || (src_frq == 0)) {
@@ -559,7 +551,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 		printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
-	clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+	clrsetbits_le32(&clk->clk_div_peric4, AUDIO_1_RATIO_MASK,
 				(div & AUDIO_1_RATIO_MASK));
 	return 0;
 }
diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h
index 05be3cc021..7d0a5d56f0 100644
--- a/src/cpu/samsung/exynos5420/cpu.h
+++ b/src/cpu/samsung/exynos5420/cpu.h
@@ -170,7 +170,7 @@
 #define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
 
 #define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE)
-#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE)
+#define samsung_get_base_clock() ((struct exynos5420_clock *)EXYNOS5_CLOCK_BASE)
 #define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE)
 #define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE)
 #define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE)