mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware. Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -14,14 +14,10 @@
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# GNU General Public License for more details.
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#
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config BOARD_JETWAY_NF81_T56N_LF
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def_bool n
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if BOARD_JETWAY_NF81_T56N_LF
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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#select ROMCC_BOOTBLOCK
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select CPU_AMD_AGESA_FAMILY14
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select NORTHBRIDGE_AMD_AGESA_FAMILY14
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select SOUTHBRIDGE_AMD_CIMX_SB800
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@ -1,2 +1,2 @@
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#config BOARD_JETWAY_NF81_T56N_LF
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# bool"NF81_T56N_LF"
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config BOARD_JETWAY_NF81_T56N_LF
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bool "NF81_T56N_LF"
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@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI
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pci$(stripped_ahcibios_id).rom-type := optionrom
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endif
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bootblock-y += bootblock.c
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romstage-y += buildOpts.c
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romstage-y += BiosCallOuts.c
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romstage-y += OemCustomize.c
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@ -14,16 +14,14 @@
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/agesa/state_machine.h>
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#include <bootblock_common.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f71869ad/f71869ad.h>
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#include <sb_cimx.h>
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/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
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#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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void bootblock_mainboard_early_init(void)
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{
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sb_Poweron_Init();
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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