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mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK 

Warning: Not tested on hardware.

Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mike Banon 2020-02-13 16:16:01 +00:00 committed by Patrick Georgi
parent e3229a5192
commit c896df7f15
4 changed files with 6 additions and 10 deletions
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4
src/mainboard/jetway/nf81-t56n-lf/Kconfig
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@ -14,14 +14,10 @@
# GNU General Public License for more details. # GNU General Public License for more details.
# #
config BOARD_JETWAY_NF81_T56N_LF
def_bool n
if BOARD_JETWAY_NF81_T56N_LF if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS config BOARD_SPECIFIC_OPTIONS
def_bool y def_bool y
#select ROMCC_BOOTBLOCK
select CPU_AMD_AGESA_FAMILY14 select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800 select SOUTHBRIDGE_AMD_CIMX_SB800

4
src/mainboard/jetway/nf81-t56n-lf/Kconfig.name
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@ -1,2 +1,2 @@
#config BOARD_JETWAY_NF81_T56N_LF config BOARD_JETWAY_NF81_T56N_LF
# bool"NF81_T56N_LF" bool "NF81_T56N_LF"

2
src/mainboard/jetway/nf81-t56n-lf/Makefile.inc
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@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI
pci$(stripped_ahcibios_id).rom-type := optionrom pci$(stripped_ahcibios_id).rom-type := optionrom
endif endif
bootblock-y += bootblock.c
romstage-y += buildOpts.c romstage-y += buildOpts.c
romstage-y += BiosCallOuts.c romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c romstage-y += OemCustomize.c

6
src/mainboard/jetway/nf81-t56n-lf/romstage.c → src/mainboard/jetway/nf81-t56n-lf/bootblock.c
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@ -14,16 +14,14 @@
* GNU General Public License for more details. * GNU General Public License for more details.
*/ */
#include <northbridge/amd/agesa/state_machine.h> #include <bootblock_common.h>
#include <superio/fintek/common/fintek.h> #include <superio/fintek/common/fintek.h>
#include <superio/fintek/f71869ad/f71869ad.h> #include <superio/fintek/f71869ad/f71869ad.h>
#include <sb_cimx.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
void board_BeforeAgesa(struct sysinfo *cb) void bootblock_mainboard_early_init(void)
{ {
sb_Poweron_Init();
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
} }