diff --git a/src/soc/mediatek/mt8186/include/soc/rtc.h b/src/soc/mediatek/mt8186/include/soc/rtc.h
index 3a0c7cd100..a3fb7a099f 100644
--- a/src/soc/mediatek/mt8186/include/soc/rtc.h
+++ b/src/soc/mediatek/mt8186/include/soc/rtc.h
@@ -143,6 +143,7 @@ enum {
 	PMIC_RG_DCXO_CW00	= 0x0788,
 	PMIC_RG_DCXO_CW00_CLR	= 0x078C,
 	PMIC_RG_DCXO_CW02	= 0x0790,
+	PMIC_RG_DCXO_CW03	= 0x0794,
 	PMIC_RG_DCXO_CW07	= 0x079A,
 	PMIC_RG_DCXO_CW09	= 0x079E,
 	PMIC_RG_DCXO_CW11	= 0x07A2,
diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c
index 528f42b3ff..2f78be8fa6 100644
--- a/src/soc/mediatek/mt8186/rtc.c
+++ b/src/soc/mediatek/mt8186/rtc.c
@@ -13,6 +13,8 @@
 #include <soc/pmic_wrap.h>
 #include <timer.h>
 
+#define MT8186_RTC_DXCO_CAPID 0xC0
+
 /* Initialize RTC setting of using DCXO clock */
 static bool rtc_enable_dcxo(void)
 {
@@ -231,6 +233,16 @@ static void mt6366_dcxo_disable_unused(void)
 	rtc_write(PMIC_RG_DCXO_CW23, 0x0052);
 }
 
+static void rtc_set_capid(u16 capid)
+{
+	u16 read_capid;
+
+	rtc_write(PMIC_RG_DCXO_CW03, 0xFF00 | capid);
+
+	rtc_read(PMIC_RG_DCXO_CW03, &read_capid);
+	rtc_info("read back capid: %#x\n", read_capid & 0xFF);
+}
+
 /* Check RTC Initialization */
 int rtc_init(int recover)
 {
@@ -337,6 +349,8 @@ static void dcxo_init(void)
 	rtc_write(PMIC_RG_DCXO_CW09, 0x408F);
 	mdelay(5);
 
+	rtc_set_capid(MT8186_RTC_DXCO_CAPID);
+
 	mt6366_dcxo_disable_unused();
 }