soc/intel/cannonlake: Add PCIE ASL entry
This patch creates _PRT entires for each PCIE root port devices. TEST=Able to see PCIE wake device in cat /proc/acpi/wake list Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28800 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
Duncan Laurie
parent
a0729899d7
commit
c8a842b708
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@ -0,0 +1,382 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* Intel PCH PCIe support */
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Method (IRQM, 1, Serialized) {
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/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
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Name (IQAA, Package () {
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Package () { 0x0000ffff, 0, 0, 16 },
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Package () { 0x0000ffff, 1, 0, 17 },
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Package () { 0x0000ffff, 2, 0, 18 },
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Package () { 0x0000ffff, 3, 0, 19 } })
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Name (IQAP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })
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/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
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Name (IQBA, Package () {
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Package () { 0x0000ffff, 0, 0, 17 },
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Package () { 0x0000ffff, 1, 0, 18 },
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Package () { 0x0000ffff, 2, 0, 19 },
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Package () { 0x0000ffff, 3, 0, 16 } })
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Name (IQBP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })
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/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
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Name (IQCA, Package () {
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Package () { 0x0000ffff, 0, 0, 18 },
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Package () { 0x0000ffff, 1, 0, 19 },
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Package () { 0x0000ffff, 2, 0, 16 },
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Package () { 0x0000ffff, 3, 0, 17 } })
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Name (IQCP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })
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/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
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Name (IQDA, Package () {
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Package () { 0x0000ffff, 0, 0, 19 },
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Package () { 0x0000ffff, 1, 0, 16 },
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Package () { 0x0000ffff, 2, 0, 17 },
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Package () { 0x0000ffff, 3, 0, 18 } })
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Name (IQDP, Package () {
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Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },
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Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
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Switch (ToInteger (Arg0))
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{
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Case (Package () { 1, 5, 9, 13 }) {
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If (PICM) {
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Return (IQAA)
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} Else {
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Return (IQAP)
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}
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}
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Case (Package () { 2, 6, 10, 14 }) {
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If (PICM) {
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Return (IQBA)
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} Else {
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Return (IQBP)
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}
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}
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Case (Package () { 3, 7, 11, 15 }) {
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If (PICM) {
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Return (IQCA)
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} Else {
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Return (IQCP)
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}
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}
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Case (Package () { 4, 8, 12, 16 }) {
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If (PICM) {
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Return (IQDA)
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} Else {
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Return (IQDP)
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}
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}
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Default {
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If (PICM) {
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Return (IQDA)
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} Else {
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Return (IQDP)
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}
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}
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}
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}
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Device (RP01)
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{
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Name (_ADR, 0x001C0000)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP02)
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{
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Name (_ADR, 0x001C0001)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP03)
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{
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Name (_ADR, 0x001C0002)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP04)
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{
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Name (_ADR, 0x001C0003)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP05)
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{
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Name (_ADR, 0x001C0004)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP06)
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{
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Name (_ADR, 0x001C0005)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP07)
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{
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Name (_ADR, 0x001C0006)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP08)
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{
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Name (_ADR, 0x001C0007)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP09)
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{
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Name (_ADR, 0x001D0000)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP10)
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{
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Name (_ADR, 0x001D0001)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP11)
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{
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Name (_ADR, 0x001D0002)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP12)
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{
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Name (_ADR, 0x001D0003)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP13)
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{
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Name (_ADR, 0x001D0004)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP14)
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{
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Name (_ADR, 0x001D0005)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP15)
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{
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Name (_ADR, 0x001D0006)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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Device (RP16)
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{
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Name (_ADR, 0x001D0007)
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OperationRegion (RPCS, PCI_Config, 0x4c, 4)
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Field (RPCS, AnyAcc, NoLock, Preserve)
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{
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, 24,
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RPPN, 8, /* Root Port Number */
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}
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Method (_PRT)
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{
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Return (IRQM (RPPN))
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}
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}
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@ -41,6 +41,9 @@
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/* PCH HDA */
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#include "pch_hda.asl"
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/* PCIE Ports */
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#include "pcie.asl"
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/* Serial IO */
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#include "serialio.asl"
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