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soc/intel/cannonlake: Add PCIE ASL entry 

This patch creates _PRT entires for each PCIE root port devices.

TEST=Able to see PCIE wake device in cat /proc/acpi/wake list

Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik 2018-09-30 01:41:45 +05:30 committed by Duncan Laurie
parent a0729899d7
commit c8a842b708
2 changed files with 385 additions and 0 deletions
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382
src/soc/intel/cannonlake/acpi/pcie.asl Normal file
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@ -0,0 +1,382 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* Intel PCH PCIe support */
Method (IRQM, 1, Serialized) {
/* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */
Name (IQAA, Package () {
Package () { 0x0000ffff, 0, 0, 16 },
Package () { 0x0000ffff, 1, 0, 17 },
Package () { 0x0000ffff, 2, 0, 18 },
Package () { 0x0000ffff, 3, 0, 19 } })
Name (IQAP, Package () {
Package () { 0x0000ffff, 0, \_SB.PCI0.LNKA, 0 },
Package () { 0x0000ffff, 1, \_SB.PCI0.LNKB, 0 },
Package () { 0x0000ffff, 2, \_SB.PCI0.LNKC, 0 },
Package () { 0x0000ffff, 3, \_SB.PCI0.LNKD, 0 } })
/* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */
Name (IQBA, Package () {
Package () { 0x0000ffff, 0, 0, 17 },
Package () { 0x0000ffff, 1, 0, 18 },
Package () { 0x0000ffff, 2, 0, 19 },
Package () { 0x0000ffff, 3, 0, 16 } })
Name (IQBP, Package () {
Package () { 0x0000ffff, 0, \_SB.PCI0.LNKB, 0 },
Package () { 0x0000ffff, 1, \_SB.PCI0.LNKC, 0 },
Package () { 0x0000ffff, 2, \_SB.PCI0.LNKD, 0 },
Package () { 0x0000ffff, 3, \_SB.PCI0.LNKA, 0 } })
/* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */
Name (IQCA, Package () {
Package () { 0x0000ffff, 0, 0, 18 },
Package () { 0x0000ffff, 1, 0, 19 },
Package () { 0x0000ffff, 2, 0, 16 },
Package () { 0x0000ffff, 3, 0, 17 } })
Name (IQCP, Package () {
Package () { 0x0000ffff, 0, \_SB.PCI0.LNKC, 0 },
Package () { 0x0000ffff, 1, \_SB.PCI0.LNKD, 0 },
Package () { 0x0000ffff, 2, \_SB.PCI0.LNKA, 0 },
Package () { 0x0000ffff, 3, \_SB.PCI0.LNKB, 0 } })
/* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */
Name (IQDA, Package () {
Package () { 0x0000ffff, 0, 0, 19 },
Package () { 0x0000ffff, 1, 0, 16 },
Package () { 0x0000ffff, 2, 0, 17 },
Package () { 0x0000ffff, 3, 0, 18 } })
Name (IQDP, Package () {
Package () { 0x0000ffff, 0, \_SB.PCI0.LNKD, 0 },
Package () { 0x0000ffff, 1, \_SB.PCI0.LNKA, 0 },
Package () { 0x0000ffff, 2, \_SB.PCI0.LNKB, 0 },
Package () { 0x0000ffff, 3, \_SB.PCI0.LNKC, 0 } })
Switch (ToInteger (Arg0))
{
Case (Package () { 1, 5, 9, 13 }) {
If (PICM) {
Return (IQAA)
} Else {
Return (IQAP)
}
}
Case (Package () { 2, 6, 10, 14 }) {
If (PICM) {
Return (IQBA)
} Else {
Return (IQBP)
}
}
Case (Package () { 3, 7, 11, 15 }) {
If (PICM) {
Return (IQCA)
} Else {
Return (IQCP)
}
}
Case (Package () { 4, 8, 12, 16 }) {
If (PICM) {
Return (IQDA)
} Else {
Return (IQDP)
}
}
Default {
If (PICM) {
Return (IQDA)
} Else {
Return (IQDP)
}
}
}
}
Device (RP01)
{
Name (_ADR, 0x001C0000)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP02)
{
Name (_ADR, 0x001C0001)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP03)
{
Name (_ADR, 0x001C0002)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP04)
{
Name (_ADR, 0x001C0003)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP05)
{
Name (_ADR, 0x001C0004)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP06)
{
Name (_ADR, 0x001C0005)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP07)
{
Name (_ADR, 0x001C0006)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP08)
{
Name (_ADR, 0x001C0007)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP09)
{
Name (_ADR, 0x001D0000)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP10)
{
Name (_ADR, 0x001D0001)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP11)
{
Name (_ADR, 0x001D0002)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP12)
{
Name (_ADR, 0x001D0003)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP13)
{
Name (_ADR, 0x001D0004)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP14)
{
Name (_ADR, 0x001D0005)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP15)
{
Name (_ADR, 0x001D0006)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}
Device (RP16)
{
Name (_ADR, 0x001D0007)
OperationRegion (RPCS, PCI_Config, 0x4c, 4)
Field (RPCS, AnyAcc, NoLock, Preserve)
{
, 24,
RPPN, 8, /* Root Port Number */
}
Method (_PRT)
{
Return (IRQM (RPPN))
}
}

3
src/soc/intel/cannonlake/acpi/southbridge.asl
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@ -41,6 +41,9 @@
/* PCH HDA */ /* PCH HDA */
#include "pch_hda.asl" #include "pch_hda.asl"
/* PCIE Ports */
#include "pcie.asl"
/* Serial IO */ /* Serial IO */
#include "serialio.asl" #include "serialio.asl"