soc/intel: Use `PWRMBASE` over static `Index 0` for PMC

This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).

TEST=Able to build and boot Google, Rex to OS.

Without this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0

With this change:
[SPEW ]     PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/soc/intel/alderlake/pmc.c

@@ -85,7 +85,8 @@ static void soc_pmc_read_resources(struct device *dev)
 	struct resource *res;
 
 	/* Add the fixed MMIO resource */
-	mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+	mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+			PCH_PWRM_BASE_SIZE / KiB);
 
 	/* Add the fixed I/O resource */
 	res = new_resource(dev, 1);

src/soc/intel/cannonlake/pmc.c

@@ -74,7 +74,8 @@ static void soc_pmc_read_resources(struct device *dev)
 	struct resource *res;
 
 	/* Add the fixed MMIO resource */
-	mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+	mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+			PCH_PWRM_BASE_SIZE / KiB);
 
 	/* Add the fixed I/O resource */
 	res = new_resource(dev, 1);

src/soc/intel/elkhartlake/pmc.c

@@ -71,7 +71,8 @@ static void soc_pmc_read_resources(struct device *dev)
 {
 	struct resource *res;
 
-	mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+	mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+			PCH_PWRM_BASE_SIZE / KiB);
 
 	res = new_resource(dev, 1);
 	res->base = (resource_t)ACPI_BASE_ADDRESS;

src/soc/intel/jasperlake/pmc.c

@@ -71,7 +71,8 @@ static void soc_pmc_read_resources(struct device *dev)
 {
 	struct resource *res;
 
-	mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+	mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+			PCH_PWRM_BASE_SIZE / KiB);
 
 	res = new_resource(dev, 1);
 	res->base = (resource_t)ACPI_BASE_ADDRESS;

src/soc/intel/meteorlake/pmc.c

@@ -80,7 +80,8 @@ static void soc_pmc_read_resources(struct device *dev)
 	struct resource *res;
 
 	/* Add the fixed MMIO resource */
-	mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+	mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+			PCH_PWRM_BASE_SIZE / KiB);
 
 	/* Add the fixed I/O resource */
 	res = new_resource(dev, 1);

src/soc/intel/tigerlake/pmc.c

@@ -84,7 +84,8 @@ static void soc_pmc_read_resources(struct device *dev)
 	struct resource *res;
 
 	/* Add the fixed MMIO resource */
-	mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
+	mmio_resource_kb(dev, PWRMBASE, PCH_PWRM_BASE_ADDRESS / KiB,
+			PCH_PWRM_BASE_SIZE / KiB);
 
 	/* Add the fixed I/O resource */
 	res = new_resource(dev, 1);