rockchip/rk3288: Add 600MHz as an option for RK3288 APLL

BUG=chrome-os-partner:41201
BRANCH=firmware-veyron
TEST=tested with subsequent patch on mickey
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I7081d92be128f522e1a33eee6f3de9dfbbf042ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a390c927ad8ed035520c8a813db808715dc5e527
Original-Change-Id: I3ce0f7b2772c8c652b7f461749d01cc7b669b6cf
Original-Reviewed-on: https://chromium-review.googlesource.com/300616
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12134
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>

src/soc/rockchip/rk3288/clock.c

@@ -79,9 +79,11 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
 /* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */
 static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1);
 static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1);
+static const struct pll_div apll_600_cfg = PLL_DIVISORS(600*MHz, 1, 2);
 static const struct pll_div *apll_cfgs[] = {
 	[APLL_1800_MHZ] = &apll_1800_cfg,
 	[APLL_1392_MHZ] = &apll_1392_cfg,
+	[APLL_600_MHZ] = &apll_600_cfg,
 };
 
 /*******************PLL CON0 BITS***************************/

src/soc/rockchip/rk3288/include/soc/clock.h

@@ -31,6 +31,7 @@
 enum apll_frequencies {
 	APLL_1800_MHZ,
 	APLL_1392_MHZ,
+	APLL_600_MHZ,
 };
 
 /* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed. */