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Removing build warning of sb600 & rs690. 

Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5271 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Wang Qing Pei 2010-03-23 06:25:55 +00:00 committed by Zheng Bao
parent b5466b0251
commit c8c09bb239
2 changed files with 8 additions and 6 deletions
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12
src/southbridge/amd/rs690/rs690_early_setup.c
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@ -128,7 +128,7 @@ static void set_nbmc_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
/* /*
* Compliant with CIM_33's ATINB_PrepareInit * Compliant with CIM_33's ATINB_PrepareInit
*/ */
static void get_cpu_rev() static void get_cpu_rev(void)
{ {
u32 eax, ebx, ecx, edx; u32 eax, ebx, ecx, edx;
__asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx) __asm__ volatile ("cpuid":"=a" (eax), "=b"(ebx), "=c"(ecx), "=d"(edx)
@ -171,7 +171,7 @@ static u8 get_nb_rev(device_t nb_dev)
* Compliant with CIM_33's ATINB_HTInit * Compliant with CIM_33's ATINB_HTInit
* Init HT link speed/width for rs690 -- k8 link * Init HT link speed/width for rs690 -- k8 link
*****************************************/ *****************************************/
static void rs690_htinit() static void rs690_htinit(void)
{ {
/* /*
* About HT, it has been done in enumerate_ht_chain(). * About HT, it has been done in enumerate_ht_chain().
@ -229,7 +229,7 @@ static void rs690_htinit()
* Function2: DRAM and HT technology Trace mode configuration * Function2: DRAM and HT technology Trace mode configuration
* Function3: Miscellaneous configuration * Function3: Miscellaneous configuration
*******************************************************/ *******************************************************/
static void k8_optimization() static void k8_optimization(void)
{ {
device_t k8_f0, k8_f2, k8_f3; device_t k8_f0, k8_f2, k8_f3;
msr_t msr; msr_t msr;
@ -443,7 +443,7 @@ static void rs690_por_init(device_t nb_dev)
} }
/* enable CFG access to Dev8, which is the SB P2P Bridge */ /* enable CFG access to Dev8, which is the SB P2P Bridge */
static void enable_rs690_dev8() static void enable_rs690_dev8(void)
{ {
set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6);
} }
@ -453,14 +453,14 @@ static void enable_rs690_dev8()
/* /*
* Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit). * Compliant with CIM_33's AtiNBInitEarlyPost (AtiInitNBBeforePCIInit).
*/ */
static void rs690_before_pci_init() static void rs690_before_pci_init(void)
{ {
} }
/* /*
* The calling sequence is same as CIM. * The calling sequence is same as CIM.
*/ */
static void rs690_early_setup() static void rs690_early_setup(void)
{ {
device_t nb_dev = PCI_DEV(0, 0, 0); device_t nb_dev = PCI_DEV(0, 0, 0);
printk(BIOS_INFO, "rs690_early_setup()\n"); printk(BIOS_INFO, "rs690_early_setup()\n");

2
src/southbridge/amd/sb600/sb600_smbus.h
View File

@ -58,5 +58,7 @@
#define axindxp_reg(reg, mask, val) \ #define axindxp_reg(reg, mask, val) \
alink_ax_indx(1, (reg), (mask), (val)) alink_ax_indx(1, (reg), (mask), (val))
int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
#endif #endif