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nb/i945/gma.c: correct VSYNC end offset 

According to "G45: Volume 3: Display Register Intel ® 965G Express
Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the
VSYNC end should start at bit 16. This is also how Linux (at least 4.4)
sets this register, which can be seen with intel-gpu-tools.

TESTED on Lenovo thinkpad X60 (it does not change anything).

Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17015
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This commit is contained in:
Arthur Heymans 2016-10-13 14:12:45 +02:00 committed by Alexander Couzens
parent 968292b8e1
commit c8c73a68be
1 changed files with 1 additions and 1 deletions
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2
src/northbridge/intel/i945/gma.c
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@ -275,7 +275,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
| (vactive + bottom_border - 1));
write32(pmmio + VSYNC(1),
(vactive + bottom_border + vfront_porch + vsync - 1)
((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
| (vactive + bottom_border + vfront_porch - 1));
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)