1. Fix pirq routing table setting for GA-2761GXDK.
2. Southbridge PCIe slots are working correctly now. 3. Disable keyboard & mouse ports for GA-2761GXDK. Signed-off-by: Morgan Tsai <my_tsai@sis.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2976 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Morgan Tsai
Carl-Daniel Hailfinger
parent
74b29b9e33
commit
c8cf4ad422
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@ -269,12 +269,12 @@ chip northbridge/amd/amdk8/root_complex
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # Keyboard
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device pnp 2e.5 off # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # Mouse
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device pnp 2e.6 off # Mouse
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irq 0x70 = 12
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end
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device pnp 2e.8 off # MIDI
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@ -75,7 +75,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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addr &= ~15;
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/* This table must be betweeen 0xf0000 & 0x100000 */
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printk_info("Writing IRQ routing tables to 0x%x...\n", addr);
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printk_info("Writing IRQ routing tables to 0x%x...", addr);
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pirq = (void *)(addr);
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v = (uint8_t *)(addr);
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@ -83,8 +83,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq->signature = PIRQ_SIGNATURE;
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pirq->version = PIRQ_VERSION;
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pirq->rtr_bus = bus_sis966[0];
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pirq->rtr_devfn = ((sbdn+6)<<3)|0;
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pirq->rtr_bus = 0;
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pirq->rtr_devfn = PCI_DEVFN(2, 0);
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pirq->exclusive_irqs = 0;
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@ -98,80 +98,72 @@ unsigned long write_pirq_routing_table(unsigned long addr)
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pirq_info = (void *) ( &pirq->checksum + 1);
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slot_num = 0;
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write_pirq_info(pirq_info, 0, PCI_DEVFN(2, 0), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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pirq_info++; slot_num++;
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pirq->size = 32 + 16 * slot_num;
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for (i = 0; i < pirq->size; i++)
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sum += v[i];
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sum = pirq->checksum - sum;
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if (sum != pirq->checksum) {
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pirq->checksum = sum;
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}
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printk_info("done.\n");
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{
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device_t dev;
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dev = dev_find_slot(0, PCI_DEVFN(2,0));
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if (dev) {
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if (dev) {
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/* initialize PCI interupts - these assignments depend
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on the PCB routing of PINTA-D
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PINTA = IRQ10
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PINTB = IRQ11
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PINTC = IRQ5
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PINTD = IRQ5
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PINTC = NA
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PINTD = IRQ10
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PINTE = IRQ11
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PINTF = IRQ5
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PINTG = IRQ10
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PINTH = IRQ5
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PINTG = NA
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PINTH = IRQ7
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*/
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int i;
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uint8_t reg[8]={0x41,0x42,0x43,0x44,0x60,0x61,0x62,0x63};
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uint8_t irq[8]={0x0A,0X0B,0X05,0X05,0X0B,0X05,0X0A,0X0A};
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uint8_t irq[8]={0x0A,0X0B,0X0,0X0a,0X0B,0X05,0X0,0X07};
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for(i=0;i<8;i++)
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pci_write_config8(dev, reg[i], irq[i]);
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}
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} // endif
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printk_debug("Setting Onboard SiS Southbridge\n");
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/*
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* Non-layout for GA-2761GX
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*
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dev = dev_find_slot(0, PCI_DEVFN(2,5)); // 5513 (IDE)
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pci_write_config8(dev, 0x3C, 0x0A);
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*/
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dev = dev_find_slot(0, PCI_DEVFN(3,0)); // USB 1.1
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pci_write_config8(dev, 0x3C, 0x0B);
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dev = dev_find_slot(0, PCI_DEVFN(3,1)); // USB 1.1
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pci_write_config8(dev, 0x3C, 0x05);
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dev = dev_find_slot(0, PCI_DEVFN(3,3)); // USB 2.0
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pci_write_config8(dev, 0x3C, 0x0A);
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pci_write_config8(dev, 0x3C, 0x07);
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dev = dev_find_slot(0, PCI_DEVFN(4,0)); // 191 (LAN)
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pci_write_config8(dev, 0x3C, 0x05);
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pci_write_config8(dev, 0x3C, 0x0A);
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dev = dev_find_slot(0, PCI_DEVFN(5,0)); // 1183 (SATA)
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pci_write_config8(dev, 0x3C, 0x0B);
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dev = dev_find_slot(0, PCI_DEVFN(6,0)); // PCI-E
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pci_write_config8(dev, 0x3C, 0x0A);
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dev = dev_find_slot(0, PCI_DEVFN(7,0)); // PCI-E
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pci_write_config8(dev, 0x3C, 0x0A);
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/*
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* Non-layout for GA-2761GX
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*
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dev = dev_find_slot(0, PCI_DEVFN(15,0)); // Azalia
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pci_write_config8(dev, 0x3C, 0x05);
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*/
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}
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//pci bridge
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write_pirq_info(pirq_info, bus_sis966[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
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pirq_info++; slot_num++;
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pirq->size = 32 + 16 * slot_num;
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for (i = 0; i < pirq->size; i++)
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sum += v[i];
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sum = pirq->checksum - sum;
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if (sum != pirq->checksum) {
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pirq->checksum = sum;
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}
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printk_info("done.\n");
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printk_debug("pirq routing table, size=%d\n", pirq->size);
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for (i = 0; i < pirq->size; i+=4)
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printk_debug("%.2x%.2x%.2x%.2x\n", v[i+3],v[i+2],v[i+1],v[i]);
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return (unsigned long) pirq_info;
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@ -151,7 +151,7 @@ static const uint8_t SiS_NB_init[56][3]={
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{0x45, 0x00 ,0xFF}, //Reg 0x45
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{0x46, 0x00 ,0x90}, //Reg 0x46
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{0x47, 0x00 ,0xA0}, //Reg 0x47
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//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable
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//{0x4C, 0xFF ,0x09}, //Reg 0x4C // SiS307 enable
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{0x4E, 0x00 ,0x00}, //Reg 0x4E
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{0x4F, 0x00 ,0x02}, //Reg 0x4F
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{0x5B, 0x00 ,0x44}, //Reg 0x5B
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@ -195,7 +195,7 @@ static const uint8_t SiS_NB_init[56][3]={
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};
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static const uint8_t SiS_NBAGP_init[34][3]={
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{0xCF, 0xDF, 0x00}, //HT issue
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{0xCF, 0xDF, 0x00}, //HT issue
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{0x06, 0xDF, 0x20},
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{0x1E, 0xDF, 0x20},
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{0x50, 0x00, 0x02},
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@ -228,7 +228,7 @@ static const uint8_t SiS_NBAGP_init[34][3]={
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{0xBF, 0xF9, 0x06},
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{0xBA, 0x00, 0x61},
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{0xBD, 0x7F, 0x80},
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{0x00, 0x00, 0x00} //End of table
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{0x00, 0x00, 0x00} //End of table
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};
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static const uint8_t SiS_ACPI_2_init[56][3]={
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@ -298,7 +298,7 @@ static const uint8_t SiS_SiS1183_init[44][3]={
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{0x2E, 0x00, 0x83},
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{0x2F, 0x00, 0x11},
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{0x90, 0x00, 0x40},
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{0x91, 0x00, 0x00}, // set mode
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{0x91, 0x00, 0x00}, // set mode
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{0x50, 0x00, 0xA2},
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{0x52, 0x00, 0xA2},
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{0x55, 0x00, 0x96},
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@ -313,7 +313,7 @@ static const uint8_t SiS_SiS1183_init[44][3]={
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{0x85, 0x00, 0xB3},
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{0x86, 0x00, 0x72},
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{0x87, 0x00, 0x40},
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{0x88, 0x00, 0xDE}, // after set mode
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{0x88, 0x00, 0xDE}, // after set mode
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{0x89, 0x00, 0xB3},
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{0x8A, 0x00, 0x72},
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{0x8B, 0x00, 0x40},
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@ -334,7 +334,7 @@ static const uint8_t SiS_SiS1183_init[44][3]={
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{0xA1, 0x00, 0x15},
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{0xA2, 0x00, 0x15},
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{0xA3, 0x00, 0x15},
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{0x00, 0x00, 0x00} //End of table
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{0x00, 0x00, 0x00} //End of table
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};
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/* In => Share Memory size
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@ -411,7 +411,7 @@ void sis_init_stage1(void)
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i++;
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};
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// ========================== NBPCIE =============================
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Disable Internal GUI enable bit
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temp8 = pci_read_config8(dev, 0x4C);
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GUI_En = temp8 & 0x10;
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pci_write_config8(dev, 0x4C, temp8 & (!0x10));
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@ -425,19 +425,19 @@ void sis_init_stage1(void)
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pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
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i++;
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};
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0); //Restore Internal GUI enable bit
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temp8 = pci_read_config8(dev, 0x4C);
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pci_write_config8(dev, 0x4C, temp8 | GUI_En);
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return;
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return;
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}
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void sis_init_stage2(void)
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{
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device_t dev;
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msr_t msr;
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device_t dev;
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msr_t msr;
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int i;
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uint8_t temp8;
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uint16_t temp16;
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@ -509,19 +509,36 @@ void sis_init_stage2(void)
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// ========================== Misc =============================
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printk_debug("Init Misc -------->\n");
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
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// PCI Device Enable
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pci_write_config8(dev, 0x7C, 0x03); // bit0=0 : enable audio controller(), bit1=1 : disable modem
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pci_write_config8(dev, 0x76, pci_read_config8(dev, 0x76)|0x30); // SM bus enable, PCIEXP Controller 1 and 2 disable
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pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable
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/* R77h Internal PCI Device Enable 1 (Power On Value = 0h)
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* bit5 : USB Emulation (1=enable)
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* bit3 : Internal Keyboard Controller Port Access Control enable (1=enable)
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* bit2 : Reserved
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* bit1 : Mask USB A20M# Event (1:K8, 0:P4/K7)
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*/
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pci_write_config8(dev, 0x77, 0x2E);
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/* R7Ch Internal PCI Device Enable 2 (Power On Value = 0h)
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* bit4 : SATA Controller Enable (0=enable)
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* bit3 : IDE Controller Enable (0=enable)
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* bit2 : MAC Controller Enable (0=enable)
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* bit1 : MODEM Controller Enable (1=disable)
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* bit0 : AC97 Controller Enable (1=disable)
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*/
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pci_write_config8(dev, 0x7C, 0x03);
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/* R7Eh Enable Azalia (Power On Value = 08h)
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* bit3 : Azalia Controller Enable (0=enable)
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*/
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pci_write_config8(dev, 0x7E, 0x00); // azalia controller enable
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temp8=inb(0x878)|0x4; //bit2=1 enable Azalia =0 enable AC97
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outb(temp8, 0x878); // ACPI select AC97 or HDA controller
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printk_debug("Audio select %x\n",inb(0x878));
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dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0);
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if(!dev){
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if (!dev)
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print_debug("SiS 1183 does not exist !!");
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}
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// SATA Set Mode
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pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
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