diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 2da9230970..d4c54a5159 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -37,6 +37,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select PCIEXP_ASPM
 	select PCIEXP_CLK_PM
 	select PCIEXP_COMMON_CLOCK
+	select PCIEXP_L1_SUB_STATE
 	select PSP_DISABLE_POSTCODES
 	select SOC_AMD_CEZANNE
 	select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c
index a83db6cd1f..e1c78da449 100644
--- a/src/mainboard/google/guybrush/port_descriptors.c
+++ b/src/mainboard/google/guybrush/port_descriptors.c
@@ -16,6 +16,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.device_number = PCI_SLOT(WLAN_DEVFN),
 		.function_number = PCI_FUNC(WLAN_DEVFN),
 		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ0,
 		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@@ -28,6 +30,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.device_number = PCI_SLOT(SD_DEVFN),
 		.function_number = PCI_FUNC(SD_DEVFN),
 		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ1,
 		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@@ -40,6 +44,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.device_number = PCI_SLOT(WWAN_DEVFN),
 		.function_number = PCI_FUNC(WWAN_DEVFN),
 		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ2,
 		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}
@@ -52,6 +58,8 @@ static const fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = {
 		.device_number = PCI_SLOT(NVME_DEVFN),
 		.function_number = PCI_FUNC(NVME_DEVFN),
 		.link_aspm = ASPM_L1,
+		.link_aspm_L1_1 = true,
+		.link_aspm_L1_2 = true,
 		.turn_off_unused_lanes = true,
 		.clk_req = CLK_REQ3,
 		.port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122}