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AGESA f14: Fix MemContext buffer parser for AmdInitPost() 

Memory training data that is saved as part of S3 feature in SPI
flash can be used to bypass training on normal boot path as well.

When RegisterSize is 3 in the register playback tables, no register is
saved or restored. Instead a function is called to do certain things in
the save and resume sequence. Previously, this was overlooked, and the
pointer containing the current OrMask was still incremented by 3 bytes.

Change-Id: I7221a03d5a4e442817911ba4862e3c0e8fa4a500
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki 2017-03-27 19:00:24 +03:00
parent 8bd6c53874
commit c91ab1cfce
1 changed files with 7 additions and 3 deletions
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10
src/vendorcode/amd/agesa/f14/Proc/Mem/Main/mmMemRestore.c
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@ -347,7 +347,9 @@ MemMRestoreDqsTimings (
if (!MemMSetCSRNb (&NBArray[Node], Reg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & Reg->RegisterList[j].AndMask)) {
return FALSE; // Restore fails
}
OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 : Reg->RegisterList[j].Type.RegisterSize;
if (Reg->RegisterList[j].Type.RegisterSize != 3)
OrMask += (Reg->RegisterList[j].Type.RegisterSize == 0) ? 4 :
Reg->RegisterList[j].Type.RegisterSize;
}
if (MaxNode < Node) {
@ -370,7 +372,9 @@ MemMRestoreDqsTimings (
if (!MemMSetCSRNb (&NBArray[Node], CReg->SpecialCases, PciAddress, *((UINT32 *) OrMask) & CReg->RegisterList[j].AndMask)) {
return FALSE; // Restore fails
}
OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 : CReg->RegisterList[j].Type.RegisterSize;
if (CReg->RegisterList[j].Type.RegisterSize != 3)
OrMask += (CReg->RegisterList[j].Type.RegisterSize == 0) ? 4 :
CReg->RegisterList[j].Type.RegisterSize;
}
}
} else if (((State == ST_PRE_ESR) && (Device.CommonDeviceHeader->Type == DEV_TYPE_MSR_PRE_ESR)) ||
@ -606,4 +610,4 @@ MemMCreateS3NbBlock (
}
}
}
}
}