GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/ironlake: Drop redundant clear of SLP_TYP 

Bits are already cleared in southbridge_detect_s3_resume().

Change-Id: If8bb85abacd59c7968876906e126300c9e4314e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-19 07:09:14 +02:00
parent 3051a9ecfa
commit c92c5e5450
2 changed files with 0 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/northbridge/intel/ironlake/raminit.c
View File

@ -4698,14 +4698,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
if (!s3resume)
save_timings(&info);
if (s3resume && cbmem_wasnot_inited) {
u32 reg32;
printk(BIOS_ERR, "Failed S3 resume.\n");
ram_check_nodie(1 * MiB);
/* Clear SLP_TYPE. */
reg32 = inl(DEFAULT_PMBASE + 0x04);
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
/* Failed S3 resume, reset to come up cleanly */
full_reset();
}

10
src/northbridge/intel/ironlake/romstage.c
View File

@ -24,7 +24,6 @@
*/
void mainboard_romstage_entry(void)
{
u32 reg32;
int s3resume = 0;
u8 spd_addrmap[4] = {};
@ -60,14 +59,5 @@ void mainboard_romstage_entry(void)
intel_early_me_status();
if (s3resume) {
/*
* Clear SLP_TYPE. This will break stage2 but
* we care for that when we get there.
*/
reg32 = inl(DEFAULT_PMBASE + 0x04);
outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
}
romstage_handoff_init(s3resume);
}