GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA,binaryPI boards: Move common PCBA in ASL 

Change-Id: I9d502882c4ddb54af1da42a41591804da2cee0ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-02-14 00:06:39 +02:00
parent c308f021d2
commit c92efa3363
41 changed files with 8 additions and 89 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/acpi/dsdt_top.asl
View File

@ -30,3 +30,11 @@ Method (_PIC, 1)
/* Remember the OS' IRQ routing choice. */
PICM = Arg0
}
#if CONFIG(MMCONF_SUPPORT)
/* Base address of PCIe config space */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
/* Length of PCIe config space, 1MB each bus */
Name(PCLN, CONFIG_MMCONF_LENGTH)
#endif

4
src/mainboard/amd/gardenia/acpi/mainboard.asl
View File

@ -1,4 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */

3
src/mainboard/amd/gardenia/dsdt.asl
View File

@ -18,9 +18,6 @@ DefinitionBlock (
/* global NVS and variables */
#include <globalnvs.asl>
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* Describe the USB Overcurrent pins */
#include "acpi/usb_oc.asl"

1
src/mainboard/amd/inagua/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

2
src/mainboard/amd/olivehill/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

4
src/mainboard/amd/padmelon/acpi/mainboard.asl
View File

@ -1,4 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */

3
src/mainboard/amd/padmelon/dsdt.asl
View File

@ -16,9 +16,6 @@ DefinitionBlock (
/* global NVS and variables */
#include <globalnvs.asl>
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* Describe the USB Overcurrent pins */
#include "acpi/usb_oc.asl"

2
src/mainboard/amd/parmer/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

1
src/mainboard/amd/persimmon/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

1
src/mainboard/amd/south_station/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

2
src/mainboard/amd/thatcher/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

1
src/mainboard/amd/union_station/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

1
src/mainboard/asrock/e350m1/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

2
src/mainboard/asrock/imb-a180/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

7
src/mainboard/asus/a88xm-e/acpi/mainboard.asl
View File

@ -1,7 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Base address of PCIe config space */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
/* Length of PCIe config space, 1MB each bus */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
/* Base address of HPET table */

3
src/mainboard/asus/a88xm-e/dsdt.asl
View File

@ -13,9 +13,6 @@ DefinitionBlock (
{ /* Start of ASL file */
#include <acpi/dsdt_top.asl>
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* Describe the USB Overcurrent pins */
#include "acpi/usb_oc.asl"

2
src/mainboard/asus/am1i-a/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

4
src/mainboard/asus/f2a85-m/acpi/mainboard.asl
View File

@ -1,4 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */

3
src/mainboard/asus/f2a85-m/dsdt.asl
View File

@ -13,9 +13,6 @@ DefinitionBlock (
{ /* Start of ASL file */
#include <acpi/dsdt_top.asl>
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* Describe the USB Overcurrent pins */
#include "acpi/usb_oc.asl"

2
src/mainboard/bap/ode_e20XX/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

2
src/mainboard/biostar/a68n_5200/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

2
src/mainboard/biostar/am1ml/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

1
src/mainboard/elmex/pcm205400/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

1
src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

2
src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

1
src/mainboard/google/kahlee/variants/aleena/include/variant/acpi/mainboard.asl
View File

@ -1,4 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

9
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl
View File

@ -1,9 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Base address of PCIe config space */
Name (PCBA, CONFIG_MMCONF_BASE_ADDRESS)
/* Length of PCIe config space, 1MB each bus */
Name (PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
/* Base address of HPET table */

1
src/mainboard/google/kahlee/variants/careena/include/variant/acpi/mainboard.asl
View File

@ -1,4 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

1
src/mainboard/google/kahlee/variants/grunt/include/variant/acpi/mainboard.asl
View File

@ -1,4 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

1
src/mainboard/google/kahlee/variants/liara/include/variant/acpi/mainboard.asl
View File

@ -1,4 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

1
src/mainboard/google/kahlee/variants/nuwani/include/variant/acpi/mainboard.asl
View File

@ -1,4 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

1
src/mainboard/google/kahlee/variants/treeya/include/variant/acpi/mainboard.asl
View File

@ -1,4 +1,3 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/acpi/mainboard.asl>
#include <baseboard/acpi/audio.asl>

2
src/mainboard/hp/abm/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

2
src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

1
src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

2
src/mainboard/lenovo/g505s/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

1
src/mainboard/lippert/frontrunner-af/dsdt.asl
View File

@ -13,7 +13,6 @@ DefinitionBlock (
{ /* Start of ASL file */
#include <acpi/dsdt_top.asl>
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
/* USB overcurrent mapping pins. */
Name(UOM0, 0)

4
src/mainboard/msi/ms7721/acpi/mainboard.asl
View File

@ -1,4 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */

3
src/mainboard/msi/ms7721/dsdt.asl
View File

@ -14,9 +14,6 @@ DefinitionBlock (
#include <acpi/dsdt_top.asl>
#include <arch/x86/acpi/debug.asl> /* Include global debug methods if needed */
/* Globals for the platform */
#include "acpi/mainboard.asl"
/* PCI IRQ mapping for the Southbridge */
#include <southbridge/amd/agesa/hudson/acpi/pcie.asl>

1
src/mainboard/pcengines/apu1/acpi/mainboard.asl
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Scope(\_SI) {
Method(_SST, 1) {

2
src/mainboard/pcengines/apu2/acpi/mainboard.asl
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
/* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)