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Fix the M57SLI routing table, as apparently set up from LinuxBIOS on 

that board. Shift PCIe pin numbers downwards, and PCI int pins upwards.
This puts both PCI slots' int A and PCIe 16x int A into the right
position.

Signed-off-by: Torsten Duwe <duwe@lst.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Torsten Duwe 2007-11-05 22:35:01 +00:00 committed by Carl-Daniel Hailfinger
parent a358892e2c
commit c931625bab
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/gigabyte/m57sli/mptable.c
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@ -129,13 +129,13 @@ void *smp_write_config_table(void *v)
for(j=7; j>=2; j--) {
if(!bus_mcp55[j]) continue;
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (1+j+i)%4);
}
}
for(j=0; j<2; j++)
for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x06+j)<<2)|i, apicid_mcp55, 0x10 + (2+i+j)%4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], ((0x07+j)<<2)|i, apicid_mcp55, 0x10 + (3+i+j)%4);
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/