soc/amd/stoneyridge: Expand 48MHz for both osc out signals
There are typically two configurable oscillator outputs available on APUs or FCHs. Convert the enable function to work with either one. BUG=b:none. TEST=Build and boot grunt. Change-Id: I4b89b1e3b7963472471e34897bdd00176dbdb914 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/c/31386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -186,6 +186,7 @@
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#define MISC_CLK_CNTL1 0x40
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#define CG1PLL_FBDIV_TEST BIT(26)
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#define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */
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#define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */
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/* XHCI_PM Registers: 0xfed81c00 */
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#define XHCI_PM_INDIRECT_INDEX 0x48
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@ -477,7 +478,7 @@ struct soc_power_reg {
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void enable_aoac_devices(void);
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void sb_enable_rom(void);
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void configure_stoneyridge_i2c(void);
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void sb_clk_output_48Mhz(void);
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void sb_clk_output_48Mhz(u32 osc);
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void sb_disable_4dw_burst(void);
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void sb_enable(struct device *dev);
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void southbridge_final(void *chip_info);
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@ -389,20 +389,28 @@ static void sb_enable_legacy_io(void)
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pm_write32(PM_DECODE_EN, reg | LEGACY_IO_EN);
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}
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void sb_clk_output_48Mhz(void)
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void sb_clk_output_48Mhz(u32 osc)
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{
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u32 ctrl;
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u32 *misc_clk_cntl_1_ptr = (u32 *)(uintptr_t)(MISC_MMIO_BASE
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+ MISC_CLK_CNTL1);
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/*
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* Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
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* 48Mhz will be on ball AP13 (FT3b package)
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* Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M)
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* or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz.
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*/
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ctrl = read32(misc_clk_cntl_1_ptr);
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/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
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ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
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switch (osc) {
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case 1:
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ctrl &= ~OSCOUT1_CLK_OUTPUT_ENB;
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break;
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case 2:
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ctrl &= ~OSCOUT2_CLK_OUTPUT_ENB;
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break;
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default:
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return; /* do nothing if invalid */
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}
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write32(misc_clk_cntl_1_ptr, ctrl);
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}
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