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google/reef: Update chromeos.fmd file 

1. Mark 256KiB at end of BIOS region as unusable BIOS region is
memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it
accordingly in fmd file.
2. Use up holes in RW region for RW_A and RW_B.
3. Fill up holes in RO with UNUSED regions.

BUG=chrome-os-partner:54672

Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15313
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2016-06-22 11:00:22 -07:00
parent 203fe7278a
commit c948746c21
1 changed files with 22 additions and 8 deletions
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30
src/mainboard/google/reef/chromeos.fmd
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@ -9,8 +9,10 @@ FLASH 16M {
RO_FRID_PAD@0x4840 0x7c0 RO_FRID_PAD@0x4840 0x7c0
COREBOOT(CBFS)@0x5000 0x17b000 COREBOOT(CBFS)@0x5000 0x17b000
GBB@0x180000 0x40000 GBB@0x180000 0x40000
RO_UNUSED_1@0x1c0000 0x400000
# logical boot partition 2. Remove with updated CSE # logical boot partition 2. Remove with updated CSE
SIGN_CSE@0x5c0000 0x10000 SIGN_CSE@0x5c0000 0x10000
RO_UNUSED_2@0x5d0000 0x30000
} }
} }
MISC_RW@0x800000 0x1a000 { MISC_RW@0x800000 0x1a000 {
@ -22,18 +24,30 @@ FLASH 16M {
} }
RW_VPD@0x18000 0x2000 RW_VPD@0x18000 0x2000
} }
RW_SECTION_A@0x81a000 0x173000 { RW_SECTION_A@0x81a000 0x28f800 {
VBLOCK_A@0x0 0x10000 VBLOCK_A@0x0 0x10000
FW_MAIN_A(CBFS)@0x10000 0x162fc0 FW_MAIN_A(CBFS)@0x10000 0x27f7c0
RW_FWID_A@0x172fc0 0x40 RW_FWID_A@0x28f7c0 0x40
} }
RW_SECTION_B@0x98d000 0x173000 { RW_SECTION_B@0xaa9800 0x28f800 {
VBLOCK_B@0x0 0x10000 VBLOCK_B@0x0 0x10000
FW_MAIN_B(CBFS)@0x10000 0x162fc0 FW_MAIN_B(CBFS)@0x10000 0x27f7c0
RW_FWID_B@0x172fc0 0x40 RW_FWID_B@0x28f7c0 0x40
} }
RW_NVRAM@0xb00000 0x6000 RW_NVRAM@0xd39000 0x6000
RW_LEGACY(CBFS)@0xb06000 0x200000 RW_LEGACY(CBFS)@0xd3f000 0x200000
BIOS_UNUSABLE@0xf3f000 0x40000
DEVICE_EXTENSION@0xf7f000 0x80000 DEVICE_EXTENSION@0xf7f000 0x80000
# Currently, it is required that the BIOS region be a multiple of 8KiB.
# This is required so that the recovery mechanism can find SIGN_CSE
# region aligned to 4K at the center of BIOS region. Since the
# descriptor at the beginning uses 4K and BIOS starts at an offset of
# 4K, a hole of 4K is created towards the end of the flash to compensate
# for the size requirement of BIOS region.
# FIT tool thus creates descriptor with following regions:
# Descriptor --> 0 to 4K
# BIOS --> 4K to 0xf7f000
# Device ext --> 0xf7f000 to 0xfff000
UNUSED_HOLE@0xfff000 0x1000
} }