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SIO: Add smsc/sch4037 superio support 

Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/562
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh 2012-02-07 20:31:40 +08:00 committed by Marc Jones
parent ea52223f53
commit c94940cd64
7 changed files with 285 additions and 0 deletions
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3
src/superio/smsc/Kconfig
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@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Ronald G. Minnich
## Copyright (C) 2012 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@ -39,3 +40,5 @@ config SUPERIO_SMSC_KBC1100
bool
config SUPERIO_SMSC_SMSCSUPERIO
bool
config SUPERIO_SMSC_SCH4037
bool

2
src/superio/smsc/Makefile.inc
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@ -2,6 +2,7 @@
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Ronald G. Minnich
## Copyright (C) 2012 Advanced Micro Devices, Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
@ -28,3 +29,4 @@ subdirs-y += lpc47n227
subdirs-y += sio10n268
subdirs-y += kbc1100
subdirs-y += smscsuperio
subdirs-y += sch4037

20
src/superio/smsc/sch4037/Makefile.inc Normal file
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@ -0,0 +1,20 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2012 Advanced Micro Devices, Inc.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
#
ramstage-$(CONFIG_SUPERIO_SMSC_SCH4037) += superio.c

34
src/superio/smsc/sch4037/chip.h Normal file
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@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_SCH_4037_CHIP_H
#define SUPERIO_SCH_4037_CHIP_H
#include <pc80/keyboard.h>
#include <uart8250.h>
struct chip_operations;
extern struct chip_operations superio_smsc_sch4037_ops;
struct superio_smsc_sch4037_config {
struct pc_keyboard keyboard;
};
#endif //SUPERIO_SCH_4037_CHIP_H

34
src/superio/smsc/sch4037/sch4037.h Normal file
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@ -0,0 +1,34 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef SUPERIO_SCH_4037_H
#define SUPERIO_SCH_4037_H
#define SCH4037_FDD 0 /* FDD */
#define SCH4037_LPT 3 /* LPT */
#define SMSCSUPERIO_SP1 4 /* Com1 */
#define SMSCSUPERIO_SP2 5 /* Com2 */
#define SCH4037_RTC 6 /* RTC */
#define SCH4037_KBC 7 /* KBC */
#define SCH4037_HWM 8 /* HWM */
#define SCH4037_RUNTIME 0x0A /* Runtime */
#define SCH4037_XBUS 0x0B /* X-BUS */
#endif //SUPERIO_SCH_4037_H

69
src/superio/smsc/sch4037/sch4037_early_init.c Normal file
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@ -0,0 +1,69 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/romcc_io.h>
#include "sch4037.h"
static inline void pnp_enter_conf_state(device_t dev)
{
unsigned port = dev>>8;
outb(0x55, port);
}
static void pnp_exit_conf_state(device_t dev)
{
unsigned port = dev>>8;
outb(0xaa, port);
}
static inline void sch4037_early_init(unsigned port)
{
device_t dev;
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_enter_conf_state(dev);
/* Auto power management */
pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */
pnp_write_config(dev, 0x23, 0 );
/* Enable SMSC UART 0 */
dev = PNP_DEV(port, SMSCSUPERIO_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE);
pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4);
/* Enabled High speed, disabled MIDI support. */
pnp_write_config(dev, 0xF0, 0x02);
pnp_set_enable(dev, 1);
/* Enable keyboard */
dev = PNP_DEV(port, SCH4037_KBC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */
pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */
pnp_set_enable(dev, 1);
pnp_exit_conf_state(dev);
}

123
src/superio/smsc/sch4037/superio.c Normal file
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@ -0,0 +1,123 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* RAM driver for the SMSC KBC1100 Super I/O chip */
#include <arch/io.h>
#include <device/device.h>
#include <device/pnp.h>
#include <console/console.h>
#include <device/smbus.h>
#include <string.h>
#include <bitops.h>
#include <uart8250.h>
#include <pc80/keyboard.h>
#include <stdlib.h>
#include "chip.h"
#include "sch4037.h"
/* Forward declarations */
static void enable_dev(device_t dev);
static void sch4037_pnp_set_resources(device_t dev);
static void sch4037_pnp_enable_resources(device_t dev);
static void sch4037_pnp_enable(device_t dev);
static void sch4037_init(device_t dev);
static void pnp_enter_conf_state(device_t dev);
static void pnp_exit_conf_state(device_t dev);
struct chip_operations superio_smsc_sch4037_ops = {
CHIP_NAME("SMSC SCH4037 Super I/O")
.enable_dev = enable_dev,
};
static struct device_operations ops = {
.read_resources = pnp_read_resources,
.set_resources = sch4037_pnp_set_resources,
.enable_resources = sch4037_pnp_enable_resources,
.enable = sch4037_pnp_enable,
.init = sch4037_init,
};
static struct pnp_info pnp_dev_info[] = {
{ &ops, SCH4037_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, },
};
static void enable_dev(device_t dev)
{
printk(BIOS_SPEW, "file '%s',line %d, %s()\n", __FILE__, __LINE__, __func__);
pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
}
static void sch4037_pnp_set_resources(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_resources(dev);
pnp_exit_conf_state(dev);
}
static void sch4037_pnp_enable_resources(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_enable_resources(dev);
pnp_exit_conf_state(dev);
}
static void sch4037_pnp_enable(device_t dev)
{
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
if(dev->enabled) {
pnp_set_enable(dev, 1);
}
else {
pnp_set_enable(dev, 0);
}
pnp_exit_conf_state(dev);
}
static void sch4037_init(device_t dev)
{
struct superio_smsc_sch4037_config *conf = dev->chip_info;
struct resource *res0, *res1;
if (!dev->enabled) {
return;
}
switch(dev->path.pnp.device) {
case SCH4037_KBC:
res0 = find_resource(dev, PNP_IDX_IO0);
res1 = find_resource(dev, PNP_IDX_IO1);
pc_keyboard_init(&conf->keyboard);
break;
}
}
static void pnp_enter_conf_state(device_t dev)
{
outb(0x55, dev->path.pnp.port);
}
static void pnp_exit_conf_state(device_t dev)
{
outb(0xaa, dev->path.pnp.port);
}