mainboard: Clear up remaining SIO_PORT from Kconfig
Push back any board specific values back into romstage.c #defines and drop any remaining fragments of CONFIG_SIO_PORT in-tree. Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6045 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Edward O'Callaghan
Kyösti Mälkki
parent
401b8accf8
commit
c94d73e0e6
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@ -72,10 +72,6 @@ config RAMBASE
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hex
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default 0x200000
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config SIO_PORT
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hex
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default 0x2e
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config DRIVERS_PS2_KEYBOARD
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bool
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default y
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@ -37,8 +37,7 @@
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#include "Platform.h"
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#include <arch/cpu.h>
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#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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u32 agesawrapper_amdinitmmio (void);
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u32 agesawrapper_amdinitreset (void);
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@ -58,7 +57,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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post_code(0x30);
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sch4037_early_init (CONFIG_SIO_PORT);
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sch4037_early_init(0x2e);
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/* Detect SMSC SIO1036 LPC Debug Card status */
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if (detect_sio1036_chip(0x4E)) {
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@ -69,10 +69,6 @@ config RAMBASE
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hex
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default 0x200000
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config SIO_PORT
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hex
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default 0x2e
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config ONBOARD_VGA_IS_PRIMARY
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bool
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default y
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@ -39,7 +39,7 @@
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#include "SBPLATFORM.h"
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#define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1)
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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@ -89,8 +89,4 @@ config VGA_BIOS_ID
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string
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default "1002,9712"
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config SIO_PORT
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hex
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default 0x2E
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endif #BOARD_AVALUE_EAX_785E
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@ -52,6 +52,7 @@
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#include "northbridge/amd/amdfam10/debug.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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#define CLK_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void activate_spd_rom(const struct mem_controller *ctrl)
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{
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@ -102,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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enable_rs780_dev8();
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sb800_clk_output_48Mhz();
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w83627hf_set_clksel_48(PNP_DEV(CONFIG_SIO_PORT, 0));
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w83627hf_set_clksel_48(CLK_DEV);
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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@ -35,10 +35,6 @@ config MAX_CPUS
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int
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default 16
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config SIO_PORT
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hex
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default 0x164e
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config SMBIOS_SYSTEM_ENCLOSURE_TYPE
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hex
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default 0x09 # This is a mobile platform
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@ -44,6 +44,8 @@
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#include "gpio.h"
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#include <arch/stages.h>
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#define SIO_PORT 0x164e
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static inline void reset_system(void)
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{
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hard_reset();
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@ -69,7 +71,7 @@ static void pch_enable_lpc(void)
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/* Map a range for the runtime registers to the LPC bus. */
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pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181);
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if (sio1007_enable_uart_at(CONFIG_SIO_PORT)) {
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if (sio1007_enable_uart_at(SIO_PORT)) {
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pci_write_config16(dev, LPC_EN,
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lpc_config | COMA_LPC_EN);
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}
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@ -77,7 +79,7 @@ static void pch_enable_lpc(void)
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static void setup_sio_gpios(void)
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{
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const u16 port = CONFIG_SIO_PORT;
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const u16 port = SIO_PORT;
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const u16 runtime_port = 0x180;
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/* Turn on configuration mode. */
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@ -72,13 +72,6 @@ config RAMBASE
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hex
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default 0x200000
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config SIO_PORT
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hex
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default 0x164E
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help
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though UARTs are on the NUVOTON BMC, port 0x164E
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PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
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config DRIVERS_PS2_KEYBOARD
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bool
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default y
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@ -35,6 +35,10 @@
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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/* though UARTs are on the NUVOTON BMC, port 0x164E
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* PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
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*/
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#define SIO_PORT 0x164e
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void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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{
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@ -49,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
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report_bist_failure(bist);
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sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */
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wpcm450_enable_dev(WPCM450_SP1, CONFIG_SIO_PORT, CONFIG_TTYS0_BASE);
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wpcm450_enable_dev(WPCM450_SP1, SIO_PORT, CONFIG_TTYS0_BASE);
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sb7xx_51xx_disable_wideio(0);
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post_code(0x34);
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@ -75,13 +75,6 @@ config RAMBASE
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hex
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default 0x200000
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config SIO_PORT
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hex
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default 0x164E
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help
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though UARTs are on the NUVOTON BMC, port 0x164E
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PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
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config DRIVERS_PS2_KEYBOARD
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bool
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default y
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@ -72,13 +72,6 @@ config RAMBASE
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hex
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default 0x200000
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config SIO_PORT
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hex
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default 0x164E
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help
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though UARTs are on the NUVOTON BMC, port 0x164E
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PS2 keyboard and mouse are on SUPERIO_WINBOND_W83627DHG, port 0x2E
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config DRIVERS_PS2_KEYBOARD
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bool
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default y
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