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skylake: ACPI: Clean up GPIO controller 

Switch the GPIO controller to use the PCR functions that are
defined in pcr.asl.

Have the default memory regions declare a size of zero and
be fixed up in the _CRS in order to fix compile issues on
some versions of iasl.

BUG=chrome-os-partner:44622
BRANCH=none
TEST=emerge-glados coreboot

Change-Id: Ic82fcb00285aeb2515e24001ef69a882c3df1417
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: be24d9ccd9db62ca694f3a67436af25a73f59c5a
Original-Change-Id: I13acd891427f467e289d5671add5617befef4380
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295951
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11538
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2015-08-27 17:15:00 -07:00 committed by Patrick Georgi
parent e32da955b3
commit c97106fd48
1 changed files with 27 additions and 37 deletions
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64
src/soc/intel/skylake/acpi/gpio.asl
View File

@ -18,54 +18,44 @@
* Foundation, Inc.
*/
/* PCR Register Access Methods PCR Dword Read arg0: PID arg1: Offset */
Method (PCRR, 2, Serialized)
{
Add (ShiftLeft (Arg0, PCR_PORTID_SHIFT), Arg1, Local0)
Add (PCH_PCR_BASE_ADDRESS, Local0, Local0)
OperationRegion (PCR0, SystemMemory, Local0, 0x4)
Field(PCR0, DWordAcc, Lock, Preserve)
{
Offset(0x00),
DAT0, 32
}
Return (DAT0)
}
Device (GPIO)
{
/* GPIO Controller */
Name (_HID, "INT344B")
Name (_UID, 1)
Name (_DDN, "GPIO Controller")
Name (RBUF, ResourceTemplate()
{
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R0)
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R1)
Memory32Fixed (ReadWrite, 0, GPIO_BASE_SIZE, _R3)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, _R4)
{
GPIO_IRQ14,
}
Memory32Fixed (ReadWrite, 0, 0, COM0)
Memory32Fixed (ReadWrite, 0, 0, COM1)
Memory32Fixed (ReadWrite, 0, 0, COM3)
Interrupt (ResourceConsumer, Level, ActiveLow, Shared,,, GIRQ)
{ 0 }
})
Method (_CRS, 0, NotSerialized) /* _CRS: Current Resource Settings */
Method (_CRS, 0, NotSerialized)
{
CreateDWordField (^RBUF, ^_R0._BAS, COM0)
CreateDWordField (^RBUF, ^_R1._BAS, COM1)
CreateDWordField (^RBUF, ^_R3._BAS, COM3)
CreateDWordField (^RBUF, ^_R4._INT, IRQN)
/* GPIO Community 0 */
CreateDWordField (^RBUF, ^COM0._BAS, BAS0)
CreateDWordField (^RBUF, ^COM0._LEN, LEN0)
Store (^^PCRB (PID_GPIOCOM0), BAS0)
Store (GPIO_BASE_SIZE, LEN0)
Store (Add (PCH_PCR_BASE_ADDRESS,
ShiftLeft (PID_GPIOCOM0, PCR_PORTID_SHIFT)), COM0)
Store (Add (PCH_PCR_BASE_ADDRESS,
ShiftLeft (PID_GPIOCOM1, PCR_PORTID_SHIFT)), COM1)
Store (Add (PCH_PCR_BASE_ADDRESS,
ShiftLeft (PID_GPIOCOM3, PCR_PORTID_SHIFT)), COM3)
Store (And (PCRR (PID_GPIOCOM0, MISCCFG_OFFSET),
GPIO_DRIVER_IRQ_ROUTE_MASK), Local0)
/* GPIO Community 1 */
CreateDWordField (^RBUF, ^COM1._BAS, BAS1)
CreateDWordField (^RBUF, ^COM1._LEN, LEN1)
Store (^^PCRB (PID_GPIOCOM1), BAS1)
Store (GPIO_BASE_SIZE, LEN1)
/* GPIO Community 3 */
CreateDWordField (^RBUF, ^COM3._BAS, BAS3)
CreateDWordField (^RBUF, ^COM3._LEN, LEN3)
Store (^^PCRB (PID_GPIOCOM3), BAS3)
Store (GPIO_BASE_SIZE, LEN3)
CreateDWordField (^RBUF, ^GIRQ._INT, IRQN)
And (^^PCRR (PID_GPIOCOM0, MISCCFG_OFFSET),
GPIO_DRIVER_IRQ_ROUTE_MASK, Local0)
If (LEqual (Local0, GPIO_DRIVER_IRQ_ROUTE_IRQ14)) {
Store (GPIO_IRQ14, IRQN)