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lippert/toucan-af: Switch away from AGESA_LEGACY 

NOTE: Some code was currently left behind that may be
required for certain type of board reboots. A followup
patch will address this.

Change-Id: I8fb89fb82c3a3608bb84b29319eb793605538996
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-03-04 07:48:42 +02:00
parent 5d883661ae
commit c97b0607ff
3 changed files with 22 additions and 92 deletions
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1
src/mainboard/lippert/toucan-af/Kconfig
View File

@ -17,7 +17,6 @@ if BOARD_LIPPERT_TOUCAN_AF
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select AGESA_LEGACY
select CPU_AMD_AGESA_FAMILY14
select NORTHBRIDGE_AMD_AGESA_FAMILY14
select SOUTHBRIDGE_AMD_CIMX_SB800

14
src/mainboard/lippert/toucan-af/OemCustomize.c
View File

@ -22,7 +22,7 @@
#include "Filecode.h"
#include <string.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/state_machine.h>
#define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE
@ -42,7 +42,7 @@
**/
/*---------------------------------------------------------------------------------------*/
static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly)
{
AGESA_STATUS Status;
VOID *BrazosPcieComplexListPtr;
@ -138,7 +138,6 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr;
InitEarly->GnbConfig.PsppPolicy = 0;
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------
@ -152,13 +151,14 @@ PCIe_COMPLEX_DESCRIPTOR Brazos = {
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = {
HW_RXEN_SEED (ANY_SOCKET, ANY_CHANNEL, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B, 0x3B),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2),
NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1),
PSO_END
};
const struct OEM_HOOK OemCustomize = {
.InitEarly = OemInitEarly,
};
void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost)
{
InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable;
}

99
src/mainboard/lippert/toucan-af/romstage.c
View File

@ -13,95 +13,26 @@
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/x86/mtrr.h>
#include <cpu/amd/car.h>
#include <northbridge/amd/agesa/agesawrapper.h>
#include <northbridge/amd/agesa/agesa_helper.h>
#include <cpu/x86/bist.h>
#include <northbridge/amd/agesa/state_machine.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627dhg/w83627dhg.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
#include <sb_cimx.h>
#include "SBPLATFORM.h"
#include "cbmem.h"
#include <cpu/amd/mtrr.h>
#include <cpu/amd/agesa/s3_resume.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void board_BeforeAgesa(struct sysinfo *cb)
{
u32 val;
/* Must come first to enable PCI MMCONF. */
amd_initmmio();
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_Poweron_Init();
post_code(0x31);
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
/* Halt if there was a built in self test failure */
post_code(0x34);
report_bist_failure(bist);
/* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
post_code(0x37);
agesawrapper_amdinitreset();
post_code(0x39);
agesawrapper_amdinitearly();
int s3resume = acpi_is_wakeup_s3();
if (!s3resume) {
post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
* hang, looks like DRAM re-init goes wrong, don't know why. */
val = agesawrapper_amdinitpost();
if (val == 7) /* fatal, amdinitenv below is going to hang */
outb(0x06, 0x0cf9); /* reset system harder instead */
post_code(0x42);
agesawrapper_amdinitenv();
amd_initenv();
} else { /* S3 detect */
printk(BIOS_INFO, "S3 detected\n");
post_code(0x60);
agesawrapper_amdinitresume();
agesawrapper_amds3laterestore();
post_code(0x61);
prepare_for_resume();
}
post_code(0x50);
copy_and_run();
printk(BIOS_ERR, "Error: copy_and_run() returned!\n");
post_code(0x54); /* Should never see this post code. */
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
}
#if 0
post_code(0x40);
/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
* hang, looks like DRAM re-init goes wrong, don't know why. */
val = agesawrapper_amdinitpost();
if (val == 7) /* fatal, amdinitenv below is going to hang */
outb(0x06, 0x0cf9); /* reset system harder instead */
post_code(0x42);
agesawrapper_amdinitenv();
#endif