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lynxpoint/broadwell: fix PCH power optimizer 

Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.

The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.

Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output

Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18385
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Matt DeVillier 2017-02-16 11:36:16 -06:00 committed by Martin Roth
parent ee6a612eb2
commit c97e042a9b
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/broadwell/lpc.c
View File

@ -262,7 +262,7 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
/* Power Optimizer */ /* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080), REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005), REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),

2
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -347,7 +347,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff), RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001), RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */ RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */ RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */ RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */