intel/i945: Use "IS_ENABLED" for fsbclk & memclk
Change-Id: I3213a8664955239b10bcf1784ce1ba5e0d95688b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16958 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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@ -106,10 +106,8 @@ void sdram_dump_mchbar_registers(void)
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static int memclk(void)
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{
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int offset = 0;
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#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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offset++;
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#endif
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int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0;
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switch (((MCHBAR32(CLKCFG) >> 4) & 7) - offset) {
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case 1: return 400;
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case 2: return 533;
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@ -119,29 +117,26 @@ static int memclk(void)
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return -1;
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}
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#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
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static u16 fsbclk(void)
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{
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switch (MCHBAR32(CLKCFG) & 7) {
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case 0: return 400;
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case 1: return 533;
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case 3: return 667;
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default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
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if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) {
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switch (MCHBAR32(CLKCFG) & 7) {
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case 0: return 400;
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case 1: return 533;
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case 3: return 667;
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default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
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}
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return 0xffff;
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} else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) {
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switch (MCHBAR32(CLKCFG) & 7) {
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case 0: return 1066;
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case 1: return 533;
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case 2: return 800;
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default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
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}
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return 0xffff;
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}
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return 0xffff;
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}
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#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
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static u16 fsbclk(void)
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{
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switch (MCHBAR32(CLKCFG) & 7) {
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case 0: return 1066;
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case 1: return 533;
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case 2: return 800;
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default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
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}
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return 0xffff;
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}
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#endif
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static int sdram_capabilities_max_supported_memory_frequency(void)
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{
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