intel/fsp2_0: Move temporary RAM to .bss with FSP_USES_CB_STACK

The documentation for StackBase and StackSize in FSPM_ARCH_UPD is
confusing. Previously the region was shared for heap and stack,
starting with FSP2.1 only for heap (or 'temporary RAM') for HOBs.

Moving the allocation outside DCACHE_BSP_STACK_SIZE allows use of
stack guards and reduces amount of reserved CAR for bootblock and
verstage, as the new allocation in .bss is only taken in romstage.

BUG=b:140268415

Change-Id: I4cffcc73a89cb97ab7759dd373196ce9753a6307
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Kyösti Mälkki 2019-09-03 07:03:39 +03:00
parent c563d34fc1
commit c9871505f1
2 changed files with 20 additions and 12 deletions

View File

@ -152,6 +152,11 @@ config FSP_USES_CB_STACK
without reinitializing stack pointer. This feature is without reinitializing stack pointer. This feature is
supported Icelake onwards. supported Icelake onwards.
config FSP_TEMP_RAM_SIZE
hex
default 0x10000
depends on FSP_USES_CB_STACK
config VERIFY_HOBS config VERIFY_HOBS
bool "Verify the FSP hand-off-blocks" bool "Verify the FSP hand-off-blocks"
default n default n

View File

@ -34,6 +34,8 @@
#include <fsp/memory_init.h> #include <fsp/memory_init.h>
#include <types.h> #include <types.h>
static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
/* TPM MRC hash functionality depends on vboot starting before memory init. */ /* TPM MRC hash functionality depends on vboot starting before memory init. */
_Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) || _Static_assert(!CONFIG(FSP2_0_USES_TPM_MRC_HASH) ||
CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), CONFIG(VBOOT_STARTS_IN_BOOTBLOCK),
@ -161,23 +163,13 @@ static enum cb_err check_region_overlap(const struct memranges *ranges,
return CB_SUCCESS; return CB_SUCCESS;
} }
static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd,
const struct memranges *memmap) const struct memranges *memmap)
{ {
uintptr_t stack_begin; uintptr_t stack_begin;
uintptr_t stack_end; uintptr_t stack_end;
/*
* FSP 2.1 version would use same stack as coreboot instead of
* setting up seprate stack frame. FSP 2.1 would not relocate stack
* top and does not reinitialize stack pointer.
*/
if (CONFIG(FSP_USES_CB_STACK)) {
arch_upd->StackBase = (void *)_car_stack_start;
arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE;
return CB_SUCCESS;
}
/* /*
* FSPM_UPD passed here is populated with default values * FSPM_UPD passed here is populated with default values
* provided by the blob itself. We let FSPM use top of CAR * provided by the blob itself. We let FSPM use top of CAR
@ -197,8 +189,19 @@ static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd,
bool s3wake, uint32_t fsp_version, bool s3wake, uint32_t fsp_version,
const struct memranges *memmap) const struct memranges *memmap)
{ {
if (setup_fsp_stack_frame(arch_upd, memmap)) /*
* FSP 2.1 version would use same stack as coreboot instead of
* setting up separate stack frame. FSP 2.1 would not relocate stack
* top and does not reinitialize stack pointer. The parameters passed
* as StackBase and StackSize are actually for temporary RAM and HOBs
* and are not related to FSP stack at all.
*/
if (CONFIG(FSP_USES_CB_STACK)) {
arch_upd->StackBase = temp_ram;
arch_upd->StackSize = sizeof(temp_ram);
} else if (setup_fsp_stack_frame(arch_upd, memmap)) {
return CB_ERR; return CB_ERR;
}
fsp_fill_mrc_cache(arch_upd, fsp_version); fsp_fill_mrc_cache(arch_upd, fsp_version);