mb/intel/adlrvp: enable ECT for LP5 memory

On ADLRVP with LP5  memory, MRC team recommends enabling ECT(Early
Command Training) to avoid hang during boot process.

BRANCH=firmware-brya-14505.B
TEST=Booted to OS on ADLRVP with LP5 memory.

Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I2472707825bbbdd8e5c12a714e0d40ea0b458838
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/mainboard/intel/adlrvp/memory.c

@@ -137,7 +137,7 @@ static const struct mb_cfg lp5_mem_config = {
 		.ddr7 = { .dqs0 = 0, .dqs1 = 1 }
 	},
 
-	.ect = false, /* Early Command Training */
+	.ect = true, /* Early Command Training */
 
 	.LpDdrDqDqsReTraining = 1,