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mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000

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Temporary workaround for S0ix issues related to FSP's handling of 0 value.
When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this
value which seems to be causing issues with s0ix.

This is still being debugged and a final solution will be made when available

BUG=b:159151238
TEST=flash image with workaround to volteer and verify that s0ix
cycles correctly.

Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Brandon Breitenstein 2020-06-10 17:04:29 -07:00 committed by Duncan Laurie
parent 097e449013
commit c9a3451305
1 changed files with 6 additions and 6 deletions
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12
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -150,12 +150,12 @@ chip soc/intel/tigerlake
register "TcssAuxOri" = "1"
register "IomTypeCPortPadCfg[0]" = "0x090E000A"
register "IomTypeCPortPadCfg[1]" = "0x090E000D"
register "IomTypeCPortPadCfg[2]" = "0x0"
register "IomTypeCPortPadCfg[3]" = "0x0"
register "IomTypeCPortPadCfg[4]" = "0x0"
register "IomTypeCPortPadCfg[5]" = "0x0"
register "IomTypeCPortPadCfg[6]" = "0x0"
register "IomTypeCPortPadCfg[7]" = "0x0"
register "IomTypeCPortPadCfg[2]" = "0x09000000"
register "IomTypeCPortPadCfg[3]" = "0x09000000"
register "IomTypeCPortPadCfg[4]" = "0x09000000"
register "IomTypeCPortPadCfg[5]" = "0x09000000"
register "IomTypeCPortPadCfg[6]" = "0x09000000"
register "IomTypeCPortPadCfg[7]" = "0x09000000"
# D3Hot and D3Cold for TCSS
register "TcssD3HotEnable" = "1"