src/: Remove g_ prefixes and _g suffixes from variables
These were often used to distinguish CAR_GLOBAL variables that weren't directly usable. Since we're getting rid of this special case, also get rid of the marker. This change was created using coccinelle and the following script: @match@ type T; identifier old =~ "^(g_.*|.*_g)$"; @@ old @script:python global_marker@ old << match.old; new; @@ new = old if old[0:2] == "g_": new = new[2:] if new[-2:] == "_g": new = new[:-2] coccinelle.new = new @@ identifier match.old, global_marker.new; @@ - old + new @@ type T; identifier match.old, global_marker.new; @@ - T old; + T new; @@ type T; identifier match.old, global_marker.new; @@ - T old + T new = ...; There were some manual fixups: Some code still uses the global/local variable naming scheme, so keep g_* there, and some variable names weren't completely rewritten. Change-Id: I4936ff9780a0d3ed9b8b539772bc48887f8d5eed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Patrick Georgi
parent
ae64f22e8d
commit
c9b13594eb
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@ -19,8 +19,8 @@
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#include <commonlib/helpers.h>
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#include <delay.h>
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static u32 g_timer_fsb;
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static u32 g_timer_tsc;
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static u32 timer_fsb;
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static u32 timer_tsc;
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/* This is not an architectural MSR. */
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#define MSR_PLATFORM_INFO 0xce
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@ -98,8 +98,8 @@ static void resolve_timebase(void)
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ret = get_fsb_tsc(&fsb, &ratio);
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if (ret == 0) {
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u32 tsc = 100 * DIV_ROUND_CLOSEST(ratio * fsb, 100);
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g_timer_fsb = fsb;
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g_timer_tsc = tsc;
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timer_fsb = fsb;
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timer_tsc = tsc;
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return;
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}
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@ -109,27 +109,27 @@ static void resolve_timebase(void)
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printk(BIOS_ERR, "CPU not supported\n");
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/* Set some semi-ridiculous defaults. */
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g_timer_fsb = 500;
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g_timer_tsc = 5000;
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timer_fsb = 500;
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timer_tsc = 5000;
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return;
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}
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u32 get_timer_fsb(void)
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{
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if (g_timer_fsb > 0)
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return g_timer_fsb;
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if (timer_fsb > 0)
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return timer_fsb;
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resolve_timebase();
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return g_timer_fsb;
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return timer_fsb;
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}
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unsigned long tsc_freq_mhz(void)
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{
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if (g_timer_tsc > 0)
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return g_timer_tsc;
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if (timer_tsc > 0)
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return timer_tsc;
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resolve_timebase();
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return g_timer_tsc;
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return timer_tsc;
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}
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/**
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@ -62,7 +62,7 @@ static struct monotonic_counter {
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int initialized;
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struct mono_time time;
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uint32_t last_value;
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} mono_counter_g;
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} mono_counter;
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void timer_monotonic_get(struct mono_time *mt)
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{
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@ -70,7 +70,7 @@ void timer_monotonic_get(struct mono_time *mt)
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uint32_t usecs_elapsed;
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uint32_t timer_fsb;
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if (!mono_counter_g.initialized) {
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if (!mono_counter.initialized) {
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init_timer();
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timer_fsb = get_timer_fsb();
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/* An FSB frequency of 200Mhz provides a 20 second polling
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@ -80,22 +80,22 @@ void timer_monotonic_get(struct mono_time *mt)
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printk(BIOS_WARNING,
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"apic timer freq (%d) may be too fast.\n",
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timer_fsb);
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mono_counter_g.last_value = lapic_read(LAPIC_TMCCT);
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mono_counter_g.initialized = 1;
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mono_counter.last_value = lapic_read(LAPIC_TMCCT);
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mono_counter.initialized = 1;
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}
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timer_fsb = get_timer_fsb();
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current_tick = lapic_read(LAPIC_TMCCT);
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/* Note that the APIC timer counts down. */
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usecs_elapsed = (mono_counter_g.last_value - current_tick) / timer_fsb;
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usecs_elapsed = (mono_counter.last_value - current_tick) / timer_fsb;
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/* Update current time and tick values only if a full tick occurred. */
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if (usecs_elapsed) {
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mono_time_add_usecs(&mono_counter_g.time, usecs_elapsed);
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mono_counter_g.last_value = current_tick;
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mono_time_add_usecs(&mono_counter.time, usecs_elapsed);
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mono_counter.last_value = current_tick;
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}
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/* Save result. */
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*mt = mono_counter_g.time;
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*mt = mono_counter.time;
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}
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#endif
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@ -48,7 +48,7 @@ static struct monotonic_counter {
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int initialized;
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struct mono_time time;
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uint64_t last_value;
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} mono_counter_g;
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} mono_counter;
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void timer_monotonic_get(struct mono_time *mt)
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{
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@ -56,14 +56,14 @@ void timer_monotonic_get(struct mono_time *mt)
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uint64_t ticks_elapsed;
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unsigned long ticks_per_usec;
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if (!mono_counter_g.initialized) {
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if (!mono_counter.initialized) {
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init_timer();
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mono_counter_g.last_value = rdtscll();
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mono_counter_g.initialized = 1;
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mono_counter.last_value = rdtscll();
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mono_counter.initialized = 1;
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}
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current_tick = rdtscll();
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ticks_elapsed = current_tick - mono_counter_g.last_value;
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ticks_elapsed = current_tick - mono_counter.last_value;
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ticks_per_usec = tsc_freq_mhz();
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/* Update current time and tick values only if a full tick occurred. */
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@ -71,11 +71,11 @@ void timer_monotonic_get(struct mono_time *mt)
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uint64_t usecs_elapsed;
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usecs_elapsed = ticks_elapsed / ticks_per_usec;
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mono_time_add_usecs(&mono_counter_g.time, (long)usecs_elapsed);
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mono_counter_g.last_value = current_tick;
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mono_time_add_usecs(&mono_counter.time, (long)usecs_elapsed);
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mono_counter.last_value = current_tick;
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}
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/* Save result. */
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*mt = mono_counter_g.time;
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*mt = mono_counter.time;
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}
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#endif
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@ -65,14 +65,14 @@ struct elog_state {
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enum elog_init_state elog_initialized;
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};
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static struct elog_state g_elog_state;
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static struct elog_state elog_state;
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#define ELOG_SIZE (4 * KiB)
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static uint8_t elog_mirror_buf[ELOG_SIZE];
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static inline struct region_device *mirror_dev_get(void)
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{
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return &g_elog_state.mirror_dev.rdev;
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return &elog_state.mirror_dev.rdev;
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}
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static size_t elog_events_start(void)
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@ -83,7 +83,7 @@ static size_t elog_events_start(void)
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static size_t elog_events_total_space(void)
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{
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return region_device_sz(&g_elog_state.nv_dev) - elog_events_start();
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return region_device_sz(&elog_state.nv_dev) - elog_events_start();
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}
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static struct event_header *elog_get_event_buffer(size_t offset, size_t size)
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@ -93,8 +93,9 @@ static struct event_header *elog_get_event_buffer(size_t offset, size_t size)
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static struct event_header *elog_get_next_event_buffer(size_t size)
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{
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elog_debug("ELOG: new event at offset 0x%zx\n", g_elog_state.mirror_last_write);
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return elog_get_event_buffer(g_elog_state.mirror_last_write, size);
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elog_debug("ELOG: new event at offset 0x%zx\n",
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elog_state.mirror_last_write);
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return elog_get_event_buffer(elog_state.mirror_last_write, size);
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}
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static void elog_put_event_buffer(struct event_header *event)
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@ -105,53 +106,53 @@ static void elog_put_event_buffer(struct event_header *event)
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static size_t elog_mirror_reset_last_write(void)
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{
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/* Return previous write value. */
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size_t prev = g_elog_state.mirror_last_write;
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size_t prev = elog_state.mirror_last_write;
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g_elog_state.mirror_last_write = 0;
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elog_state.mirror_last_write = 0;
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return prev;
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}
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static void elog_mirror_increment_last_write(size_t size)
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{
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g_elog_state.mirror_last_write += size;
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elog_state.mirror_last_write += size;
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}
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static void elog_nv_reset_last_write(void)
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{
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g_elog_state.nv_last_write = 0;
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elog_state.nv_last_write = 0;
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}
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static void elog_nv_increment_last_write(size_t size)
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{
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g_elog_state.nv_last_write += size;
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elog_state.nv_last_write += size;
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}
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static void elog_nv_needs_possible_erase(void)
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{
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/* If last write is 0 it means it is already erased. */
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if (g_elog_state.nv_last_write != 0)
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g_elog_state.nv_last_write = NV_NEEDS_ERASE;
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if (elog_state.nv_last_write != 0)
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elog_state.nv_last_write = NV_NEEDS_ERASE;
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}
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static bool elog_should_shrink(void)
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{
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return g_elog_state.mirror_last_write >= g_elog_state.full_threshold;
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return elog_state.mirror_last_write >= elog_state.full_threshold;
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}
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static bool elog_nv_needs_erase(void)
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{
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return g_elog_state.nv_last_write == NV_NEEDS_ERASE;
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return elog_state.nv_last_write == NV_NEEDS_ERASE;
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}
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static bool elog_nv_needs_update(void)
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{
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return g_elog_state.nv_last_write != g_elog_state.mirror_last_write;
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return elog_state.nv_last_write != elog_state.mirror_last_write;
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}
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static size_t elog_nv_region_to_update(size_t *offset)
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{
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*offset = g_elog_state.nv_last_write;
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return g_elog_state.mirror_last_write - g_elog_state.nv_last_write;
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*offset = elog_state.nv_last_write;
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return elog_state.mirror_last_write - elog_state.nv_last_write;
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}
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/*
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@ -335,7 +336,7 @@ static void elog_nv_write(size_t offset, size_t size)
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return;
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/* Write the data to flash */
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if (rdev_writeat(&g_elog_state.nv_dev, address, offset, size) != size)
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if (rdev_writeat(&elog_state.nv_dev, address, offset, size) != size)
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printk(BIOS_ERR, "ELOG: NV Write failed at 0x%zx, size 0x%zx\n",
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offset, size);
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@ -348,11 +349,11 @@ static void elog_nv_write(size_t offset, size_t size)
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*/
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static void elog_nv_erase(void)
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{
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size_t size = region_device_sz(&g_elog_state.nv_dev);
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size_t size = region_device_sz(&elog_state.nv_dev);
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elog_debug("%s()\n", __func__);
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/* Erase the sectors in this region */
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if (rdev_eraseat(&g_elog_state.nv_dev, 0, size) != size)
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if (rdev_eraseat(&elog_state.nv_dev, 0, size) != size)
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printk(BIOS_ERR, "ELOG: erase failure.\n");
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}
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@ -411,11 +412,11 @@ static int elog_scan_flash(void)
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void *mirror_buffer;
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const struct region_device *rdev = mirror_dev_get();
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size_t size = region_device_sz(&g_elog_state.nv_dev);
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size_t size = region_device_sz(&elog_state.nv_dev);
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/* Fill memory buffer by reading from SPI */
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mirror_buffer = rdev_mmap_full(rdev);
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if (rdev_readat(&g_elog_state.nv_dev, mirror_buffer, 0, size) != size) {
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if (rdev_readat(&elog_state.nv_dev, mirror_buffer, 0, size) != size) {
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rdev_munmap(rdev, mirror_buffer);
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printk(BIOS_ERR, "ELOG: NV read failure.\n");
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return -1;
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@ -580,7 +581,7 @@ static int elog_prepare_empty(void)
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static int elog_shrink(void)
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{
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if (elog_should_shrink())
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return elog_shrink_by_size(g_elog_state.shrink_size);
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return elog_shrink_by_size(elog_state.shrink_size);
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return 0;
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}
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@ -593,12 +594,13 @@ static inline u8 *elog_flash_offset_to_address(void)
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if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED))
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return NULL;
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if (!region_device_sz(&g_elog_state.nv_dev))
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if (!region_device_sz(&elog_state.nv_dev))
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return NULL;
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/* Get a view into the read-only boot device. */
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return rdev_mmap(boot_device_ro(), region_device_offset(&g_elog_state.nv_dev),
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region_device_sz(&g_elog_state.nv_dev));
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return rdev_mmap(boot_device_ro(),
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region_device_offset(&elog_state.nv_dev),
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region_device_sz(&elog_state.nv_dev));
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}
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/*
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@ -611,7 +613,7 @@ int elog_smbios_write_type15(unsigned long *current, int handle)
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int len = sizeof(struct smbios_type15);
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uintptr_t log_address;
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size_t elog_size = region_device_sz(&g_elog_state.nv_dev);
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size_t elog_size = region_device_sz(&elog_state.nv_dev);
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if (CONFIG(ELOG_CBMEM)) {
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/* Save event log buffer into CBMEM for the OS to read */
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@ -665,7 +667,7 @@ static int elog_find_flash(void)
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{
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size_t total_size;
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size_t reserved_space = ELOG_MIN_AVAILABLE_ENTRIES * MAX_EVENT_SIZE;
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struct region_device *rdev = &g_elog_state.nv_dev;
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struct region_device *rdev = &elog_state.nv_dev;
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elog_debug("%s()\n", __func__);
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@ -688,10 +690,10 @@ static int elog_find_flash(void)
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total_size = MIN(ELOG_SIZE, region_device_sz(rdev));
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rdev_chain(rdev, rdev, 0, total_size);
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g_elog_state.full_threshold = total_size - reserved_space;
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g_elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100;
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elog_state.full_threshold = total_size - reserved_space;
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elog_state.shrink_size = total_size * ELOG_SHRINK_PERCENTAGE / 100;
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if (reserved_space > g_elog_state.shrink_size) {
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if (reserved_space > elog_state.shrink_size) {
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printk(BIOS_ERR, "ELOG: SHRINK_PERCENTAGE too small\n");
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return -1;
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}
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@ -734,7 +736,7 @@ static int elog_sync_to_nv(void)
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if (elog_scan_flash() < 0) {
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printk(BIOS_ERR, "ELOG: Sync back from NV storage failed.\n");
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elog_debug_dump_buffer("ELOG: Buffer from NV:\n");
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g_elog_state.elog_initialized = ELOG_BROKEN;
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elog_state.elog_initialized = ELOG_BROKEN;
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return -1;
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}
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@ -776,7 +778,7 @@ int elog_init(void)
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{
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void *mirror_buffer;
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size_t elog_size;
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switch (g_elog_state.elog_initialized) {
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switch (elog_state.elog_initialized) {
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case ELOG_UNINITIALIZED:
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break;
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case ELOG_INITIALIZED:
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@ -784,7 +786,7 @@ int elog_init(void)
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case ELOG_BROKEN:
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return -1;
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}
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g_elog_state.elog_initialized = ELOG_BROKEN;
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elog_state.elog_initialized = ELOG_BROKEN;
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elog_debug("elog_init()\n");
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@ -792,19 +794,20 @@ int elog_init(void)
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if (elog_find_flash() < 0)
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return -1;
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elog_size = region_device_sz(&g_elog_state.nv_dev);
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elog_size = region_device_sz(&elog_state.nv_dev);
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mirror_buffer = elog_mirror_buf;
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if (!mirror_buffer) {
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printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n");
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return -1;
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}
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mem_region_device_rw_init(&g_elog_state.mirror_dev, mirror_buffer, elog_size);
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mem_region_device_rw_init(&elog_state.mirror_dev, mirror_buffer,
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elog_size);
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||||
/*
|
||||
* Mark as initialized to allow elog_init() to be called and deemed
|
||||
* successful in the prepare/shrink path which adds events.
|
||||
*/
|
||||
g_elog_state.elog_initialized = ELOG_INITIALIZED;
|
||||
elog_state.elog_initialized = ELOG_INITIALIZED;
|
||||
|
||||
/* Load the log from flash and prepare the flash if necessary. */
|
||||
if (elog_scan_flash() < 0 && elog_prepare_empty() < 0) {
|
||||
|
|
@ -813,8 +816,8 @@ int elog_init(void)
|
|||
}
|
||||
|
||||
printk(BIOS_INFO, "ELOG: area is %zu bytes, full threshold %d,"
|
||||
" shrink size %d\n", region_device_sz(&g_elog_state.nv_dev),
|
||||
g_elog_state.full_threshold, g_elog_state.shrink_size);
|
||||
" shrink size %d\n", region_device_sz(&elog_state.nv_dev),
|
||||
elog_state.full_threshold, elog_state.shrink_size);
|
||||
|
||||
if (ENV_PAYLOAD_LOADER)
|
||||
elog_add_boot_count();
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ struct tpm_inf_dev {
|
|||
uint8_t buf[CR50_MAX_BUFSIZE + sizeof(uint8_t)];
|
||||
};
|
||||
|
||||
static struct tpm_inf_dev g_tpm_dev;
|
||||
static struct tpm_inf_dev tpm_dev;
|
||||
|
||||
__weak int tis_plat_irq_status(void)
|
||||
{
|
||||
|
|
@ -101,14 +101,14 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip)
|
|||
static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr,
|
||||
uint8_t *buffer, size_t len)
|
||||
{
|
||||
if (g_tpm_dev.addr == 0)
|
||||
if (tpm_dev.addr == 0)
|
||||
return -1;
|
||||
|
||||
/* Clear interrupt before starting transaction */
|
||||
tis_plat_irq_status();
|
||||
|
||||
/* Send the register address byte to the TPM */
|
||||
if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, &addr, 1)) {
|
||||
if (i2c_write_raw(tpm_dev.bus, tpm_dev.addr, &addr, 1)) {
|
||||
printk(BIOS_ERR, "%s: Address write failed\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -118,7 +118,7 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr,
|
|||
return -1;
|
||||
|
||||
/* Read response data from the TPM */
|
||||
if (i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr, buffer, len)) {
|
||||
if (i2c_read_raw(tpm_dev.bus, tpm_dev.addr, buffer, len)) {
|
||||
printk(BIOS_ERR, "%s: Read response failed\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -143,20 +143,20 @@ static int cr50_i2c_read(struct tpm_chip *chip, uint8_t addr,
|
|||
static int cr50_i2c_write(struct tpm_chip *chip,
|
||||
uint8_t addr, uint8_t *buffer, size_t len)
|
||||
{
|
||||
if (g_tpm_dev.addr == 0)
|
||||
if (tpm_dev.addr == 0)
|
||||
return -1;
|
||||
if (len > CR50_MAX_BUFSIZE)
|
||||
return -1;
|
||||
|
||||
/* Prepend the 'register address' to the buffer */
|
||||
g_tpm_dev.buf[0] = addr;
|
||||
memcpy(g_tpm_dev.buf + 1, buffer, len);
|
||||
tpm_dev.buf[0] = addr;
|
||||
memcpy(tpm_dev.buf + 1, buffer, len);
|
||||
|
||||
/* Clear interrupt before starting transaction */
|
||||
tis_plat_irq_status();
|
||||
|
||||
/* Send write request buffer with address */
|
||||
if (i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr, g_tpm_dev.buf, len + 1)) {
|
||||
if (i2c_write_raw(tpm_dev.bus, tpm_dev.addr, tpm_dev.buf, len + 1)) {
|
||||
printk(BIOS_ERR, "%s: Error writing to TPM\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -494,8 +494,8 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr)
|
|||
return -1;
|
||||
}
|
||||
|
||||
g_tpm_dev.bus = bus;
|
||||
g_tpm_dev.addr = dev_addr;
|
||||
tpm_dev.bus = bus;
|
||||
tpm_dev.addr = dev_addr;
|
||||
|
||||
cr50_vendor_init(chip);
|
||||
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
#include "tpm.h"
|
||||
|
||||
/* global structure for tpm chip data */
|
||||
static struct tpm_chip g_chip;
|
||||
static struct tpm_chip chip;
|
||||
|
||||
#define TPM_CMD_COUNT_BYTE 2
|
||||
#define TPM_CMD_ORDINAL_BYTE 6
|
||||
|
|
@ -35,15 +35,15 @@ int tis_open(void)
|
|||
{
|
||||
int rc;
|
||||
|
||||
if (g_chip.is_open) {
|
||||
if (chip.is_open) {
|
||||
printk(BIOS_DEBUG, "tis_open() called twice.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
rc = tpm_vendor_init(&g_chip, CONFIG_DRIVER_TPM_I2C_BUS,
|
||||
rc = tpm_vendor_init(&chip, CONFIG_DRIVER_TPM_I2C_BUS,
|
||||
CONFIG_DRIVER_TPM_I2C_ADDR);
|
||||
if (rc < 0)
|
||||
g_chip.is_open = 0;
|
||||
chip.is_open = 0;
|
||||
|
||||
if (rc)
|
||||
return -1;
|
||||
|
|
@ -53,9 +53,9 @@ int tis_open(void)
|
|||
|
||||
int tis_close(void)
|
||||
{
|
||||
if (g_chip.is_open) {
|
||||
tpm_vendor_cleanup(&g_chip);
|
||||
g_chip.is_open = 0;
|
||||
if (chip.is_open) {
|
||||
tpm_vendor_cleanup(&chip);
|
||||
chip.is_open = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
@ -76,7 +76,7 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf,
|
|||
memcpy(&count, sbuf + TPM_CMD_COUNT_BYTE, sizeof(count));
|
||||
count = be32_to_cpu(count);
|
||||
|
||||
if (!g_chip.vendor.send || !g_chip.vendor.status || !g_chip.vendor.cancel)
|
||||
if (!chip.vendor.send || !chip.vendor.status || !chip.vendor.cancel)
|
||||
return -1;
|
||||
|
||||
if (count == 0) {
|
||||
|
|
@ -89,8 +89,8 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf,
|
|||
return -1;
|
||||
}
|
||||
|
||||
ASSERT(g_chip.vendor.send);
|
||||
rc = g_chip.vendor.send(&g_chip, (uint8_t *) sbuf, count);
|
||||
ASSERT(chip.vendor.send);
|
||||
rc = chip.vendor.send(&chip, (uint8_t *) sbuf, count);
|
||||
if (rc < 0) {
|
||||
printk(BIOS_DEBUG, "tpm_transmit: tpm_send error\n");
|
||||
goto out;
|
||||
|
|
@ -98,14 +98,14 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf,
|
|||
|
||||
int timeout = 2 * 60 * 1000; /* two minutes timeout */
|
||||
while (timeout) {
|
||||
ASSERT(g_chip.vendor.status);
|
||||
uint8_t status = g_chip.vendor.status(&g_chip);
|
||||
if ((status & g_chip.vendor.req_complete_mask) ==
|
||||
g_chip.vendor.req_complete_val) {
|
||||
ASSERT(chip.vendor.status);
|
||||
uint8_t status = chip.vendor.status(&chip);
|
||||
if ((status & chip.vendor.req_complete_mask) ==
|
||||
chip.vendor.req_complete_val) {
|
||||
goto out_recv;
|
||||
}
|
||||
|
||||
if (status == g_chip.vendor.req_canceled) {
|
||||
if (status == chip.vendor.req_canceled) {
|
||||
printk(BIOS_DEBUG,
|
||||
"tpm_transmit: Operation Canceled\n");
|
||||
rc = -1;
|
||||
|
|
@ -115,15 +115,15 @@ static ssize_t tpm_transmit(const uint8_t *sbuf, size_t sbufsiz, void *rbuf,
|
|||
timeout--;
|
||||
}
|
||||
|
||||
ASSERT(g_chip.vendor.cancel);
|
||||
g_chip.vendor.cancel(&g_chip);
|
||||
ASSERT(chip.vendor.cancel);
|
||||
chip.vendor.cancel(&chip);
|
||||
printk(BIOS_DEBUG, "tpm_transmit: Operation Timed out\n");
|
||||
rc = -1; //ETIME;
|
||||
goto out;
|
||||
|
||||
out_recv:
|
||||
|
||||
rc = g_chip.vendor.recv(&g_chip, (uint8_t *) rbuf, rbufsiz);
|
||||
rc = chip.vendor.recv(&chip, (uint8_t *) rbuf, rbufsiz);
|
||||
if (rc < 0)
|
||||
printk(BIOS_DEBUG, "tpm_transmit: tpm_recv: error %d\n", rc);
|
||||
out:
|
||||
|
|
|
|||
|
|
@ -80,7 +80,7 @@ struct tpm_inf_dev {
|
|||
enum i2c_chip_type chip_type;
|
||||
};
|
||||
|
||||
static struct tpm_inf_dev g_tpm_dev;
|
||||
static struct tpm_inf_dev tpm_dev;
|
||||
|
||||
/*
|
||||
* iic_tpm_read() - read from TPM register
|
||||
|
|
@ -101,20 +101,20 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
|
|||
int rc;
|
||||
int count;
|
||||
|
||||
if (g_tpm_dev.addr == 0)
|
||||
if (tpm_dev.addr == 0)
|
||||
return -1;
|
||||
|
||||
switch (g_tpm_dev.chip_type) {
|
||||
switch (tpm_dev.chip_type) {
|
||||
case SLB9635:
|
||||
case UNKNOWN:
|
||||
/* slb9635 protocol should work in both cases */
|
||||
for (count = 0; count < MAX_COUNT; count++) {
|
||||
rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr,
|
||||
rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr,
|
||||
&addr, 1);
|
||||
if (rc == 0)
|
||||
break; /* success, break to skip sleep */
|
||||
|
||||
udelay(g_tpm_dev.sleep_short);
|
||||
udelay(tpm_dev.sleep_short);
|
||||
}
|
||||
|
||||
if (rc)
|
||||
|
|
@ -125,8 +125,8 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
|
|||
* retrieving the data
|
||||
*/
|
||||
for (count = 0; count < MAX_COUNT; count++) {
|
||||
udelay(g_tpm_dev.sleep_short);
|
||||
rc = i2c_read_raw(g_tpm_dev.bus, g_tpm_dev.addr,
|
||||
udelay(tpm_dev.sleep_short);
|
||||
rc = i2c_read_raw(tpm_dev.bus, tpm_dev.addr,
|
||||
buffer, len);
|
||||
if (rc == 0)
|
||||
break; /* success, break to skip sleep */
|
||||
|
|
@ -142,23 +142,23 @@ static int iic_tpm_read(uint8_t addr, uint8_t *buffer, size_t len)
|
|||
* retries should usually not be needed, but are kept just to
|
||||
* be safe on the safe side.
|
||||
*/
|
||||
struct i2c_msg aseg = { .flags = 0, .slave = g_tpm_dev.addr,
|
||||
struct i2c_msg aseg = { .flags = 0, .slave = tpm_dev.addr,
|
||||
.buf = &addr, .len = 1 };
|
||||
struct i2c_msg dseg = { .flags = I2C_M_RD,
|
||||
.slave = g_tpm_dev.addr,
|
||||
.slave = tpm_dev.addr,
|
||||
.buf = buffer, .len = len };
|
||||
for (count = 0; count < MAX_COUNT; count++) {
|
||||
rc = i2c_transfer(g_tpm_dev.bus, &aseg, 1) ||
|
||||
i2c_transfer(g_tpm_dev.bus, &dseg, 1);
|
||||
rc = i2c_transfer(tpm_dev.bus, &aseg, 1) ||
|
||||
i2c_transfer(tpm_dev.bus, &dseg, 1);
|
||||
if (rc == 0)
|
||||
break; /* break here to skip sleep */
|
||||
udelay(g_tpm_dev.sleep_short);
|
||||
udelay(tpm_dev.sleep_short);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* take care of 'guard time' */
|
||||
udelay(g_tpm_dev.sleep_short);
|
||||
udelay(tpm_dev.sleep_short);
|
||||
if (rc)
|
||||
return -1;
|
||||
|
||||
|
|
@ -179,14 +179,14 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len,
|
|||
}
|
||||
|
||||
/* prepare send buffer */
|
||||
g_tpm_dev.buf[0] = addr;
|
||||
memcpy(&(g_tpm_dev.buf[1]), buffer, len);
|
||||
tpm_dev.buf[0] = addr;
|
||||
memcpy(&(tpm_dev.buf[1]), buffer, len);
|
||||
|
||||
if (g_tpm_dev.addr == 0)
|
||||
if (tpm_dev.addr == 0)
|
||||
return -1;
|
||||
for (count = 0; count < max_count; count++) {
|
||||
rc = i2c_write_raw(g_tpm_dev.bus, g_tpm_dev.addr,
|
||||
g_tpm_dev.buf, len + 1);
|
||||
rc = i2c_write_raw(tpm_dev.bus, tpm_dev.addr,
|
||||
tpm_dev.buf, len + 1);
|
||||
if (rc == 0)
|
||||
break; /* success, break to skip sleep */
|
||||
|
||||
|
|
@ -194,7 +194,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len,
|
|||
}
|
||||
|
||||
/* take care of 'guard time' */
|
||||
udelay(g_tpm_dev.sleep_short);
|
||||
udelay(tpm_dev.sleep_short);
|
||||
if (rc)
|
||||
return -1;
|
||||
|
||||
|
|
@ -219,7 +219,7 @@ static int iic_tpm_write_generic(uint8_t addr, uint8_t *buffer, size_t len,
|
|||
*/
|
||||
static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len)
|
||||
{
|
||||
return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_short,
|
||||
return iic_tpm_write_generic(addr, buffer, len, tpm_dev.sleep_short,
|
||||
MAX_COUNT);
|
||||
}
|
||||
|
||||
|
|
@ -229,7 +229,7 @@ static int iic_tpm_write(uint8_t addr, uint8_t *buffer, size_t len)
|
|||
* */
|
||||
static int iic_tpm_write_long(uint8_t addr, uint8_t *buffer, size_t len)
|
||||
{
|
||||
return iic_tpm_write_generic(addr, buffer, len, g_tpm_dev.sleep_long,
|
||||
return iic_tpm_write_generic(addr, buffer, len, tpm_dev.sleep_long,
|
||||
MAX_COUNT_LONG);
|
||||
}
|
||||
|
||||
|
|
@ -479,11 +479,11 @@ int tpm_vendor_probe(unsigned int bus, uint32_t addr)
|
|||
int ret;
|
||||
long sw_run_duration = SLEEP_DURATION_PROBE_MS;
|
||||
|
||||
g_tpm_dev.chip_type = UNKNOWN;
|
||||
g_tpm_dev.bus = bus;
|
||||
g_tpm_dev.addr = addr;
|
||||
g_tpm_dev.sleep_short = SLEEP_DURATION;
|
||||
g_tpm_dev.sleep_long = SLEEP_DURATION_LONG;
|
||||
tpm_dev.chip_type = UNKNOWN;
|
||||
tpm_dev.bus = bus;
|
||||
tpm_dev.addr = addr;
|
||||
tpm_dev.sleep_short = SLEEP_DURATION;
|
||||
tpm_dev.sleep_long = SLEEP_DURATION_LONG;
|
||||
|
||||
/*
|
||||
* Probe TPM. Check if the TPM_ACCESS register's ValidSts bit is set(1)
|
||||
|
|
@ -522,11 +522,11 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr)
|
|||
return -1;
|
||||
}
|
||||
|
||||
g_tpm_dev.chip_type = UNKNOWN;
|
||||
g_tpm_dev.bus = bus;
|
||||
g_tpm_dev.addr = dev_addr;
|
||||
g_tpm_dev.sleep_short = SLEEP_DURATION;
|
||||
g_tpm_dev.sleep_long = SLEEP_DURATION_LONG;
|
||||
tpm_dev.chip_type = UNKNOWN;
|
||||
tpm_dev.bus = bus;
|
||||
tpm_dev.addr = dev_addr;
|
||||
tpm_dev.sleep_short = SLEEP_DURATION;
|
||||
tpm_dev.sleep_long = SLEEP_DURATION_LONG;
|
||||
|
||||
memset(&chip->vendor, 0, sizeof(struct tpm_vendor_specific));
|
||||
chip->is_open = 1;
|
||||
|
|
@ -547,9 +547,9 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr)
|
|||
goto out_err;
|
||||
|
||||
if (vendor == TPM_TIS_I2C_DID_VID_9645) {
|
||||
g_tpm_dev.chip_type = SLB9645;
|
||||
tpm_dev.chip_type = SLB9645;
|
||||
} else if (be32_to_cpu(vendor) == TPM_TIS_I2C_DID_VID_9635) {
|
||||
g_tpm_dev.chip_type = SLB9635;
|
||||
tpm_dev.chip_type = SLB9635;
|
||||
} else {
|
||||
printk(BIOS_DEBUG, "Vendor ID 0x%08x not recognized.\n",
|
||||
vendor);
|
||||
|
|
@ -557,8 +557,8 @@ int tpm_vendor_init(struct tpm_chip *chip, unsigned int bus, uint32_t dev_addr)
|
|||
}
|
||||
|
||||
printk(BIOS_DEBUG, "I2C TPM %u:%02x (chip type %s device-id 0x%X)\n",
|
||||
g_tpm_dev.bus, g_tpm_dev.addr,
|
||||
chip_name[g_tpm_dev.chip_type], vendor >> 16);
|
||||
tpm_dev.bus, tpm_dev.addr,
|
||||
chip_name[tpm_dev.chip_type], vendor >> 16);
|
||||
|
||||
/*
|
||||
* A timeout query to TPM can be placed here.
|
||||
|
|
|
|||
|
|
@ -106,19 +106,19 @@ bad_ctc:
|
|||
}
|
||||
|
||||
#if CONFIG(UNKNOWN_TSC_RATE)
|
||||
static u32 g_timer_tsc;
|
||||
static u32 timer_tsc;
|
||||
|
||||
unsigned long tsc_freq_mhz(void)
|
||||
{
|
||||
if (g_timer_tsc > 0)
|
||||
return g_timer_tsc;
|
||||
if (timer_tsc > 0)
|
||||
return timer_tsc;
|
||||
|
||||
g_timer_tsc = calibrate_tsc_with_pit();
|
||||
timer_tsc = calibrate_tsc_with_pit();
|
||||
|
||||
/* Set some semi-ridiculous rate if approximation fails. */
|
||||
if (g_timer_tsc == 0)
|
||||
g_timer_tsc = 5000;
|
||||
if (timer_tsc == 0)
|
||||
timer_tsc = 5000;
|
||||
|
||||
return g_timer_tsc;
|
||||
return timer_tsc;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,11 +22,11 @@
|
|||
#define LINE_BUFFER_SIZE 128
|
||||
#define READ_BUFFER_SIZE 0x100
|
||||
|
||||
static const struct region_device *g_rdev_ptr;
|
||||
static struct region_device g_rdev;
|
||||
static uint8_t g_line_buffer[LINE_BUFFER_SIZE];
|
||||
static size_t g_offset;
|
||||
static size_t g_line_offset;
|
||||
static const struct region_device *rdev_ptr;
|
||||
static struct region_device rdev;
|
||||
static uint8_t line_buffer[LINE_BUFFER_SIZE];
|
||||
static size_t offset;
|
||||
static size_t line_offset;
|
||||
|
||||
void flashconsole_init(void)
|
||||
{
|
||||
|
|
@ -36,11 +36,11 @@ void flashconsole_init(void)
|
|||
size_t len = READ_BUFFER_SIZE;
|
||||
size_t i;
|
||||
|
||||
if (fmap_locate_area_as_rdev_rw("CONSOLE", &g_rdev)) {
|
||||
if (fmap_locate_area_as_rdev_rw("CONSOLE", &rdev)) {
|
||||
printk(BIOS_INFO, "Can't find 'CONSOLE' area in FMAP\n");
|
||||
return;
|
||||
}
|
||||
size = region_device_sz(&g_rdev);
|
||||
size = region_device_sz(&rdev);
|
||||
|
||||
/*
|
||||
* We need to check the region until we find a 0xff indicating
|
||||
|
|
@ -56,7 +56,7 @@ void flashconsole_init(void)
|
|||
// Fill the buffer on first iteration
|
||||
if (i == 0) {
|
||||
len = min(READ_BUFFER_SIZE, size - offset);
|
||||
if (rdev_readat(&g_rdev, buffer, offset, len) != len)
|
||||
if (rdev_readat(&rdev, buffer, offset, len) != len)
|
||||
return;
|
||||
}
|
||||
if (buffer[i] == 0xff) {
|
||||
|
|
@ -75,29 +75,29 @@ void flashconsole_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
g_offset = offset;
|
||||
g_rdev_ptr = &g_rdev;
|
||||
offset = offset;
|
||||
rdev_ptr = &rdev;
|
||||
}
|
||||
|
||||
void flashconsole_tx_byte(unsigned char c)
|
||||
{
|
||||
if (!g_rdev_ptr)
|
||||
if (!rdev_ptr)
|
||||
return;
|
||||
|
||||
size_t region_size = region_device_sz(g_rdev_ptr);
|
||||
size_t region_size = region_device_sz(rdev_ptr);
|
||||
|
||||
g_line_buffer[g_line_offset++] = c;
|
||||
line_buffer[line_offset++] = c;
|
||||
|
||||
if (g_line_offset >= LINE_BUFFER_SIZE ||
|
||||
g_offset + g_line_offset >= region_size || c == '\n') {
|
||||
if (line_offset >= LINE_BUFFER_SIZE ||
|
||||
offset + line_offset >= region_size || c == '\n') {
|
||||
flashconsole_tx_flush();
|
||||
}
|
||||
}
|
||||
|
||||
void flashconsole_tx_flush(void)
|
||||
{
|
||||
size_t offset = g_offset;
|
||||
size_t len = g_line_offset;
|
||||
size_t offset = offset;
|
||||
size_t len = line_offset;
|
||||
size_t region_size;
|
||||
static int busy;
|
||||
|
||||
|
|
@ -107,23 +107,23 @@ void flashconsole_tx_flush(void)
|
|||
if (busy)
|
||||
return;
|
||||
|
||||
if (!g_rdev_ptr)
|
||||
if (!rdev_ptr)
|
||||
return;
|
||||
|
||||
busy = 1;
|
||||
region_size = region_device_sz(g_rdev_ptr);
|
||||
region_size = region_device_sz(rdev_ptr);
|
||||
if (offset + len >= region_size)
|
||||
len = region_size - offset;
|
||||
|
||||
if (rdev_writeat(&g_rdev, g_line_buffer, offset, len) != len)
|
||||
if (rdev_writeat(&rdev, line_buffer, offset, len) != len)
|
||||
return;
|
||||
|
||||
// If the region is full, stop future write attempts
|
||||
if (offset + len >= region_size)
|
||||
return;
|
||||
|
||||
g_offset = offset + len;
|
||||
g_line_offset = 0;
|
||||
offset = offset + len;
|
||||
line_offset = 0;
|
||||
|
||||
busy = 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -39,10 +39,10 @@
|
|||
#define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */
|
||||
|
||||
/* SPI slave structure for TPM device. */
|
||||
static struct spi_slave g_spi_slave;
|
||||
static struct spi_slave spi_slave;
|
||||
|
||||
/* Cached TPM device identification. */
|
||||
static struct tpm2_info g_tpm_info;
|
||||
static struct tpm2_info tpm_info;
|
||||
|
||||
/*
|
||||
* TODO(vbendeb): make CONFIG_DEBUG_TPM an int to allow different level of
|
||||
|
|
@ -60,7 +60,7 @@ typedef struct {
|
|||
|
||||
void tpm2_get_info(struct tpm2_info *info)
|
||||
{
|
||||
*info = g_tpm_info;
|
||||
*info = tpm_info;
|
||||
}
|
||||
|
||||
__weak int tis_plat_irq_status(void)
|
||||
|
|
@ -133,9 +133,9 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
|
|||
|
||||
if (wakeup_needed) {
|
||||
/* Just in case Cr50 is asleep. */
|
||||
spi_claim_bus(&g_spi_slave);
|
||||
spi_claim_bus(&spi_slave);
|
||||
udelay(1);
|
||||
spi_release_bus(&g_spi_slave);
|
||||
spi_release_bus(&spi_slave);
|
||||
udelay(100);
|
||||
}
|
||||
|
||||
|
|
@ -158,7 +158,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
|
|||
header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff;
|
||||
|
||||
/* CS assert wakes up the slave. */
|
||||
spi_claim_bus(&g_spi_slave);
|
||||
spi_claim_bus(&spi_slave);
|
||||
|
||||
/*
|
||||
* The TCG TPM over SPI specification introduces the notion of SPI
|
||||
|
|
@ -185,7 +185,7 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
|
|||
* to require to stall the master, this would present an issue.
|
||||
* crosbug.com/p/52132 has been opened to track this.
|
||||
*/
|
||||
spi_xfer(&g_spi_slave, header.body, sizeof(header.body), NULL, 0);
|
||||
spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0);
|
||||
|
||||
/*
|
||||
* Now poll the bus until TPM removes the stall bit. Give it up to 100
|
||||
|
|
@ -196,10 +196,10 @@ static int start_transaction(int read_write, size_t bytes, unsigned int addr)
|
|||
do {
|
||||
if (stopwatch_expired(&sw)) {
|
||||
printk(BIOS_ERR, "TPM flow control failure\n");
|
||||
spi_release_bus(&g_spi_slave);
|
||||
spi_release_bus(&spi_slave);
|
||||
return 0;
|
||||
}
|
||||
spi_xfer(&g_spi_slave, NULL, 0, &byte, 1);
|
||||
spi_xfer(&spi_slave, NULL, 0, &byte, 1);
|
||||
} while (!(byte & 1));
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -267,7 +267,7 @@ static void trace_dump(const char *prefix, uint32_t reg,
|
|||
*/
|
||||
static void write_bytes(const void *buffer, size_t bytes)
|
||||
{
|
||||
spi_xfer(&g_spi_slave, buffer, bytes, NULL, 0);
|
||||
spi_xfer(&spi_slave, buffer, bytes, NULL, 0);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -276,7 +276,7 @@ static void write_bytes(const void *buffer, size_t bytes)
|
|||
*/
|
||||
static void read_bytes(void *buffer, size_t bytes)
|
||||
{
|
||||
spi_xfer(&g_spi_slave, NULL, 0, buffer, bytes);
|
||||
spi_xfer(&spi_slave, NULL, 0, buffer, bytes);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -291,7 +291,7 @@ static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t by
|
|||
if (!start_transaction(false, bytes, reg_number))
|
||||
return 0;
|
||||
write_bytes(buffer, bytes);
|
||||
spi_release_bus(&g_spi_slave);
|
||||
spi_release_bus(&spi_slave);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -309,7 +309,7 @@ static int tpm2_read_reg(unsigned int reg_number, void *buffer, size_t bytes)
|
|||
return 0;
|
||||
}
|
||||
read_bytes(buffer, bytes);
|
||||
spi_release_bus(&g_spi_slave);
|
||||
spi_release_bus(&spi_slave);
|
||||
trace_dump("R", reg_number, bytes, buffer, 0);
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -417,7 +417,7 @@ int tpm2_init(struct spi_slave *spi_if)
|
|||
uint8_t cmd;
|
||||
int retries;
|
||||
|
||||
memcpy(&g_spi_slave, spi_if, sizeof(*spi_if));
|
||||
memcpy(&spi_slave, spi_if, sizeof(*spi_if));
|
||||
|
||||
/* clear any pending IRQs */
|
||||
tis_plat_irq_status();
|
||||
|
|
@ -474,15 +474,15 @@ int tpm2_init(struct spi_slave *spi_if)
|
|||
* structure.
|
||||
*/
|
||||
tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd));
|
||||
g_tpm_info.vendor_id = did_vid & 0xffff;
|
||||
g_tpm_info.device_id = did_vid >> 16;
|
||||
g_tpm_info.revision = cmd;
|
||||
tpm_info.vendor_id = did_vid & 0xffff;
|
||||
tpm_info.device_id = did_vid >> 16;
|
||||
tpm_info.revision = cmd;
|
||||
|
||||
printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n",
|
||||
g_tpm_info.vendor_id, g_tpm_info.device_id, g_tpm_info.revision);
|
||||
tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision);
|
||||
|
||||
/* Let's report device FW version if available. */
|
||||
if (g_tpm_info.vendor_id == 0x1ae0) {
|
||||
if (tpm_info.vendor_id == 0x1ae0) {
|
||||
int chunk_count = 0;
|
||||
size_t chunk_size;
|
||||
/*
|
||||
|
|
@ -611,7 +611,7 @@ size_t tpm2_process_command(const void *tpm2_command, size_t command_size,
|
|||
const int HEADER_SIZE = 6;
|
||||
|
||||
/* Do not try using an uninitialized TPM. */
|
||||
if (!g_tpm_info.vendor_id)
|
||||
if (!tpm_info.vendor_id)
|
||||
return 0;
|
||||
|
||||
/* Skip the two byte tag, read the size field. */
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@ struct vpd_gets_arg {
|
|||
int matched;
|
||||
};
|
||||
|
||||
struct vpd_blob g_vpd_blob;
|
||||
struct vpd_blob vpd_blob;
|
||||
|
||||
/*
|
||||
* returns the size of data in a VPD 2.0 formatted fmap region, or 0.
|
||||
|
|
@ -85,10 +85,10 @@ static void vpd_get_blob(void)
|
|||
if (ro_vpd_size == 0 && rw_vpd_size == 0)
|
||||
return;
|
||||
|
||||
g_vpd_blob.ro_base = NULL;
|
||||
g_vpd_blob.ro_size = 0;
|
||||
g_vpd_blob.rw_base = NULL;
|
||||
g_vpd_blob.rw_size = 0;
|
||||
vpd_blob.ro_base = NULL;
|
||||
vpd_blob.ro_size = 0;
|
||||
vpd_blob.rw_base = NULL;
|
||||
vpd_blob.rw_size = 0;
|
||||
|
||||
struct region_device vpd;
|
||||
|
||||
|
|
@ -101,9 +101,9 @@ static void vpd_get_blob(void)
|
|||
}
|
||||
rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET,
|
||||
region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET);
|
||||
g_vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) +
|
||||
vpd_blob.ro_base = (uint8_t *)(rdev_mmap_full(&vpd) +
|
||||
sizeof(struct google_vpd_info));
|
||||
g_vpd_blob.ro_size = ro_vpd_size;
|
||||
vpd_blob.ro_size = ro_vpd_size;
|
||||
}
|
||||
if (rw_vpd_size) {
|
||||
if (fmap_locate_area_as_rdev("RW_VPD", &vpd)) {
|
||||
|
|
@ -114,19 +114,19 @@ static void vpd_get_blob(void)
|
|||
}
|
||||
rdev_chain(&vpd, &vpd, GOOGLE_VPD_2_0_OFFSET,
|
||||
region_device_sz(&vpd) - GOOGLE_VPD_2_0_OFFSET);
|
||||
g_vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) +
|
||||
vpd_blob.rw_base = (uint8_t *)(rdev_mmap_full(&vpd) +
|
||||
sizeof(struct google_vpd_info));
|
||||
g_vpd_blob.rw_size = rw_vpd_size;
|
||||
vpd_blob.rw_size = rw_vpd_size;
|
||||
}
|
||||
g_vpd_blob.initialized = true;
|
||||
vpd_blob.initialized = true;
|
||||
}
|
||||
|
||||
const struct vpd_blob *vpd_load_blob(void)
|
||||
{
|
||||
if (g_vpd_blob.initialized == false)
|
||||
if (vpd_blob.initialized == false)
|
||||
vpd_get_blob();
|
||||
|
||||
return &g_vpd_blob;
|
||||
return &vpd_blob;
|
||||
}
|
||||
|
||||
static int vpd_gets_callback(const uint8_t *key, uint32_t key_len,
|
||||
|
|
|
|||
|
|
@ -88,7 +88,7 @@
|
|||
|
||||
static struct cse_device {
|
||||
uintptr_t sec_bar;
|
||||
} g_cse;
|
||||
} cse;
|
||||
|
||||
/*
|
||||
* Initialize the device with provided temporary BAR. If BAR is 0 use a
|
||||
|
|
@ -105,7 +105,7 @@ void heci_init(uintptr_t tempbar)
|
|||
u8 pcireg;
|
||||
|
||||
/* Assume it is already initialized, nothing else to do */
|
||||
if (g_cse.sec_bar)
|
||||
if (cse.sec_bar)
|
||||
return;
|
||||
|
||||
/* Use default pre-ram bar */
|
||||
|
|
@ -127,7 +127,7 @@ void heci_init(uintptr_t tempbar)
|
|||
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
|
||||
pci_write_config8(dev, PCI_COMMAND, pcireg);
|
||||
|
||||
g_cse.sec_bar = tempbar;
|
||||
cse.sec_bar = tempbar;
|
||||
}
|
||||
|
||||
/* Get HECI BAR 0 from PCI configuration space */
|
||||
|
|
@ -147,17 +147,17 @@ static uint32_t get_cse_bar(void)
|
|||
static uint32_t read_bar(uint32_t offset)
|
||||
{
|
||||
/* Reach PCI config space to get BAR in case CAR global not available */
|
||||
if (!g_cse.sec_bar)
|
||||
g_cse.sec_bar = get_cse_bar();
|
||||
return read32((void *)(g_cse.sec_bar + offset));
|
||||
if (!cse.sec_bar)
|
||||
cse.sec_bar = get_cse_bar();
|
||||
return read32((void *)(cse.sec_bar + offset));
|
||||
}
|
||||
|
||||
static void write_bar(uint32_t offset, uint32_t val)
|
||||
{
|
||||
/* Reach PCI config space to get BAR in case CAR global not available */
|
||||
if (!g_cse.sec_bar)
|
||||
g_cse.sec_bar = get_cse_bar();
|
||||
return write32((void *)(g_cse.sec_bar + offset), val);
|
||||
if (!cse.sec_bar)
|
||||
cse.sec_bar = get_cse_bar();
|
||||
return write32((void *)(cse.sec_bar + offset), val);
|
||||
}
|
||||
|
||||
static uint32_t read_cse_csr(void)
|
||||
|
|
@ -725,7 +725,7 @@ int send_hmrfpo_get_status_msg(void)
|
|||
|
||||
static void update_sec_bar(struct device *dev)
|
||||
{
|
||||
g_cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base;
|
||||
cse.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base;
|
||||
}
|
||||
|
||||
static void cse_set_resources(struct device *dev)
|
||||
|
|
|
|||
|
|
@ -193,7 +193,7 @@ int platform_i2c_transfer(unsigned int bus, struct i2c_msg *segments, int count)
|
|||
struct i2c_msg *seg = segments;
|
||||
int i;
|
||||
|
||||
if (bus >= g_num_i2c_buses) {
|
||||
if (bus >= num_i2c_buses) {
|
||||
printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
|
||||
bus);
|
||||
return -1;
|
||||
|
|
@ -212,7 +212,7 @@ void i2c_init(unsigned int bus)
|
|||
{
|
||||
struct tegra_i2c_regs *regs;
|
||||
|
||||
if (bus >= g_num_i2c_buses) {
|
||||
if (bus >= num_i2c_buses) {
|
||||
printk(BIOS_ERR, "%s: ERROR: invalid I2C bus (%u)\n", __func__,
|
||||
bus);
|
||||
return;
|
||||
|
|
|
|||
|
|
@ -168,6 +168,6 @@ struct tegra_i2c_regs {
|
|||
};
|
||||
check_member(tegra_i2c_regs, config_load, 0x8C);
|
||||
|
||||
extern unsigned int g_num_i2c_buses;
|
||||
extern unsigned int num_i2c_buses;
|
||||
|
||||
#endif /* __SOC_NVIDIA_TEGRA_I2C_H__ */
|
||||
|
|
|
|||
|
|
@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = {
|
|||
}
|
||||
};
|
||||
|
||||
unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
|
||||
unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
|
||||
|
|
|
|||
|
|
@ -50,4 +50,4 @@ struct tegra_i2c_bus_info tegra_i2c_info[] = {
|
|||
}
|
||||
};
|
||||
|
||||
unsigned int g_num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
|
||||
unsigned int num_i2c_buses = ARRAY_SIZE(tegra_i2c_info);
|
||||
|
|
|
|||
|
|
@ -111,7 +111,7 @@ struct ich_spi_controller {
|
|||
uint8_t fpr_max;
|
||||
};
|
||||
|
||||
static struct ich_spi_controller g_cntlr;
|
||||
static struct ich_spi_controller cntlr;
|
||||
|
||||
enum {
|
||||
SPIS_SCIP = 0x0001,
|
||||
|
|
@ -260,9 +260,9 @@ static void ich_set_bbar(uint32_t minaddr)
|
|||
uint32_t ichspi_bbar;
|
||||
|
||||
minaddr &= bbar_mask;
|
||||
ichspi_bbar = readl_(g_cntlr.bbar) & ~bbar_mask;
|
||||
ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;
|
||||
ichspi_bbar |= minaddr;
|
||||
writel_(ichspi_bbar, g_cntlr.bbar);
|
||||
writel_(ichspi_bbar, cntlr.bbar);
|
||||
}
|
||||
|
||||
#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
|
||||
|
|
@ -305,42 +305,42 @@ void spi_init(void)
|
|||
|
||||
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
|
||||
ich7_spi = get_spi_bar(dev);
|
||||
g_cntlr.ich7_spi = ich7_spi;
|
||||
g_cntlr.opmenu = ich7_spi->opmenu;
|
||||
g_cntlr.menubytes = sizeof(ich7_spi->opmenu);
|
||||
g_cntlr.optype = &ich7_spi->optype;
|
||||
g_cntlr.addr = &ich7_spi->spia;
|
||||
g_cntlr.data = (uint8_t *)ich7_spi->spid;
|
||||
g_cntlr.databytes = sizeof(ich7_spi->spid);
|
||||
g_cntlr.status = (uint8_t *)&ich7_spi->spis;
|
||||
g_cntlr.control = &ich7_spi->spic;
|
||||
g_cntlr.bbar = &ich7_spi->bbar;
|
||||
g_cntlr.preop = &ich7_spi->preop;
|
||||
g_cntlr.fpr = &ich7_spi->pbr[0];
|
||||
g_cntlr.fpr_max = 3;
|
||||
cntlr.ich7_spi = ich7_spi;
|
||||
cntlr.opmenu = ich7_spi->opmenu;
|
||||
cntlr.menubytes = sizeof(ich7_spi->opmenu);
|
||||
cntlr.optype = &ich7_spi->optype;
|
||||
cntlr.addr = &ich7_spi->spia;
|
||||
cntlr.data = (uint8_t *)ich7_spi->spid;
|
||||
cntlr.databytes = sizeof(ich7_spi->spid);
|
||||
cntlr.status = (uint8_t *)&ich7_spi->spis;
|
||||
cntlr.control = &ich7_spi->spic;
|
||||
cntlr.bbar = &ich7_spi->bbar;
|
||||
cntlr.preop = &ich7_spi->preop;
|
||||
cntlr.fpr = &ich7_spi->pbr[0];
|
||||
cntlr.fpr_max = 3;
|
||||
} else {
|
||||
ich9_spi = get_spi_bar(dev);
|
||||
g_cntlr.ich9_spi = ich9_spi;
|
||||
cntlr.ich9_spi = ich9_spi;
|
||||
hsfs = readw_(&ich9_spi->hsfs);
|
||||
g_cntlr.hsfs = hsfs;
|
||||
g_cntlr.opmenu = ich9_spi->opmenu;
|
||||
g_cntlr.menubytes = sizeof(ich9_spi->opmenu);
|
||||
g_cntlr.optype = &ich9_spi->optype;
|
||||
g_cntlr.addr = &ich9_spi->faddr;
|
||||
g_cntlr.data = (uint8_t *)ich9_spi->fdata;
|
||||
g_cntlr.databytes = sizeof(ich9_spi->fdata);
|
||||
g_cntlr.status = &ich9_spi->ssfs;
|
||||
g_cntlr.control = (uint16_t *)ich9_spi->ssfc;
|
||||
g_cntlr.bbar = &ich9_spi->bbar;
|
||||
g_cntlr.preop = &ich9_spi->preop;
|
||||
g_cntlr.fpr = &ich9_spi->pr[0];
|
||||
g_cntlr.fpr_max = 5;
|
||||
cntlr.hsfs = hsfs;
|
||||
cntlr.opmenu = ich9_spi->opmenu;
|
||||
cntlr.menubytes = sizeof(ich9_spi->opmenu);
|
||||
cntlr.optype = &ich9_spi->optype;
|
||||
cntlr.addr = &ich9_spi->faddr;
|
||||
cntlr.data = (uint8_t *)ich9_spi->fdata;
|
||||
cntlr.databytes = sizeof(ich9_spi->fdata);
|
||||
cntlr.status = &ich9_spi->ssfs;
|
||||
cntlr.control = (uint16_t *)ich9_spi->ssfc;
|
||||
cntlr.bbar = &ich9_spi->bbar;
|
||||
cntlr.preop = &ich9_spi->preop;
|
||||
cntlr.fpr = &ich9_spi->pr[0];
|
||||
cntlr.fpr_max = 5;
|
||||
|
||||
if (g_cntlr.hsfs & HSFS_FDV) {
|
||||
if (cntlr.hsfs & HSFS_FDV) {
|
||||
writel_(4, &ich9_spi->fdoc);
|
||||
g_cntlr.flmap0 = readl_(&ich9_spi->fdod);
|
||||
cntlr.flmap0 = readl_(&ich9_spi->fdod);
|
||||
writel_(0x1000, &ich9_spi->fdoc);
|
||||
g_cntlr.flcomp = readl_(&ich9_spi->fdod);
|
||||
cntlr.flcomp = readl_(&ich9_spi->fdod);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -358,9 +358,9 @@ void spi_init(void)
|
|||
static int spi_locked(void)
|
||||
{
|
||||
if (CONFIG(SOUTHBRIDGE_INTEL_I82801GX)) {
|
||||
return !!(readw_(&g_cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
|
||||
return !!(readw_(&cntlr.ich7_spi->spis) & HSFS_FLOCKDN);
|
||||
} else {
|
||||
return !!(readw_(&g_cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
|
||||
return !!(readw_(&cntlr.ich9_spi->hsfs) & HSFS_FLOCKDN);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -436,10 +436,10 @@ static int spi_setup_opcode(spi_transaction *trans)
|
|||
spi_use_out(trans, 1);
|
||||
if (!spi_locked()) {
|
||||
/* The lock is off, so just use index 0. */
|
||||
writeb_(trans->opcode, g_cntlr.opmenu);
|
||||
optypes = readw_(g_cntlr.optype);
|
||||
writeb_(trans->opcode, cntlr.opmenu);
|
||||
optypes = readw_(cntlr.optype);
|
||||
optypes = (optypes & 0xfffc) | (trans->type & 0x3);
|
||||
writew_(optypes, g_cntlr.optype);
|
||||
writew_(optypes, cntlr.optype);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -451,7 +451,7 @@ static int spi_setup_opcode(spi_transaction *trans)
|
|||
if (trans->opcode == SPI_OPCODE_WREN)
|
||||
return 0;
|
||||
|
||||
read_reg(g_cntlr.opmenu, opmenu, sizeof(opmenu));
|
||||
read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
|
||||
for (opcode_index = 0; opcode_index < ARRAY_SIZE(opmenu); opcode_index++) {
|
||||
if (opmenu[opcode_index] == trans->opcode)
|
||||
break;
|
||||
|
|
@ -463,7 +463,7 @@ static int spi_setup_opcode(spi_transaction *trans)
|
|||
return -1;
|
||||
}
|
||||
|
||||
optypes = readw_(g_cntlr.optype);
|
||||
optypes = readw_(cntlr.optype);
|
||||
optype = (optypes >> (opcode_index * 2)) & 0x3;
|
||||
if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
|
||||
optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
|
||||
|
|
@ -512,10 +512,10 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
|
|||
u16 status = 0;
|
||||
|
||||
while (timeout--) {
|
||||
status = readw_(g_cntlr.status);
|
||||
status = readw_(cntlr.status);
|
||||
if (wait_til_set ^ ((status & bitmask) == 0)) {
|
||||
if (wait_til_set)
|
||||
writew_((status & bitmask), g_cntlr.status);
|
||||
writew_((status & bitmask), cntlr.status);
|
||||
return status;
|
||||
}
|
||||
udelay(10);
|
||||
|
|
@ -528,9 +528,9 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
|
|||
|
||||
static int spi_is_multichip(void)
|
||||
{
|
||||
if (!(g_cntlr.hsfs & HSFS_FDV))
|
||||
if (!(cntlr.hsfs & HSFS_FDV))
|
||||
return 0;
|
||||
return !!((g_cntlr.flmap0 >> 8) & 3);
|
||||
return !!((cntlr.flmap0 >> 8) & 3);
|
||||
}
|
||||
|
||||
static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
||||
|
|
@ -561,7 +561,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
if (ich_status_poll(SPIS_SCIP, 0) == -1)
|
||||
return -1;
|
||||
|
||||
writew_(SPIS_CDS | SPIS_FCERR, g_cntlr.status);
|
||||
writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);
|
||||
|
||||
spi_setup_type(&trans);
|
||||
if ((opcode_index = spi_setup_opcode(&trans)) < 0)
|
||||
|
|
@ -576,7 +576,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
* issuing a transaction between WREN and DATA.
|
||||
*/
|
||||
if (!spi_locked())
|
||||
writew_(trans.opcode, g_cntlr.preop);
|
||||
writew_(trans.opcode, cntlr.preop);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -584,13 +584,13 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
|
||||
|
||||
/* Issue atomic preop cycle if needed */
|
||||
if (readw_(g_cntlr.preop))
|
||||
if (readw_(cntlr.preop))
|
||||
control |= SPIC_ACS;
|
||||
|
||||
if (!trans.bytesout && !trans.bytesin) {
|
||||
/* SPI addresses are 24 bit only */
|
||||
if (with_address)
|
||||
writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
|
||||
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
|
||||
|
||||
/*
|
||||
* This is a 'no data' command (like Write Enable), its
|
||||
|
|
@ -598,7 +598,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
* spi_setup_opcode() above. Tell the chip to send the
|
||||
* command.
|
||||
*/
|
||||
writew_(control, g_cntlr.control);
|
||||
writew_(control, cntlr.control);
|
||||
|
||||
/* wait for the result */
|
||||
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
|
||||
|
|
@ -620,7 +620,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
* and followed by other SPI commands, and this sequence is controlled
|
||||
* by the SPI chip driver.
|
||||
*/
|
||||
if (trans.bytesout > g_cntlr.databytes) {
|
||||
if (trans.bytesout > cntlr.databytes) {
|
||||
printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"
|
||||
" spi_crop_chunk()?\n");
|
||||
return -1;
|
||||
|
|
@ -634,28 +634,28 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
uint32_t data_length;
|
||||
|
||||
/* SPI addresses are 24 bit only */
|
||||
writel_(trans.offset & 0x00FFFFFF, g_cntlr.addr);
|
||||
writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
|
||||
|
||||
if (trans.bytesout)
|
||||
data_length = min(trans.bytesout, g_cntlr.databytes);
|
||||
data_length = min(trans.bytesout, cntlr.databytes);
|
||||
else
|
||||
data_length = min(trans.bytesin, g_cntlr.databytes);
|
||||
data_length = min(trans.bytesin, cntlr.databytes);
|
||||
|
||||
/* Program data into FDATA0 to N */
|
||||
if (trans.bytesout) {
|
||||
write_reg(trans.out, g_cntlr.data, data_length);
|
||||
write_reg(trans.out, cntlr.data, data_length);
|
||||
spi_use_out(&trans, data_length);
|
||||
if (with_address)
|
||||
trans.offset += data_length;
|
||||
}
|
||||
|
||||
/* Add proper control fields' values */
|
||||
control &= ~((g_cntlr.databytes - 1) << 8);
|
||||
control &= ~((cntlr.databytes - 1) << 8);
|
||||
control |= SPIC_DS;
|
||||
control |= (data_length - 1) << 8;
|
||||
|
||||
/* write it */
|
||||
writew_(control, g_cntlr.control);
|
||||
writew_(control, cntlr.control);
|
||||
|
||||
/* Wait for Cycle Done Status or Flash Cycle Error. */
|
||||
status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);
|
||||
|
|
@ -668,7 +668,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
}
|
||||
|
||||
if (trans.bytesin) {
|
||||
read_reg(g_cntlr.data, trans.in, data_length);
|
||||
read_reg(cntlr.data, trans.in, data_length);
|
||||
spi_use_in(&trans, data_length);
|
||||
if (with_address)
|
||||
trans.offset += data_length;
|
||||
|
|
@ -677,7 +677,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
|
|||
|
||||
spi_xfer_exit:
|
||||
/* Clear atomic preop now that xfer is done */
|
||||
writew_(0, g_cntlr.preop);
|
||||
writew_(0, cntlr.preop);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -685,9 +685,9 @@ spi_xfer_exit:
|
|||
/* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */
|
||||
static void ich_hwseq_set_addr(uint32_t addr)
|
||||
{
|
||||
uint32_t addr_old = readl_(&g_cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
|
||||
uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;
|
||||
|
||||
writel_((addr & 0x01FFFFFF) | addr_old, &g_cntlr.ich9_spi->faddr);
|
||||
writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);
|
||||
}
|
||||
|
||||
/* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.
|
||||
|
|
@ -701,17 +701,17 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
|
|||
uint32_t addr;
|
||||
|
||||
timeout /= 8; /* scale timeout duration to counter */
|
||||
while ((((hsfs = readw_(&g_cntlr.ich9_spi->hsfs)) &
|
||||
while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) &
|
||||
(HSFS_FDONE | HSFS_FCERR)) == 0) &&
|
||||
--timeout) {
|
||||
udelay(8);
|
||||
}
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
|
||||
|
||||
if (!timeout) {
|
||||
uint16_t hsfc;
|
||||
addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF;
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
|
||||
hsfc = readw_(&cntlr.ich9_spi->hsfc);
|
||||
printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "
|
||||
"0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
|
||||
addr, addr + len - 1, addr, len - 1,
|
||||
|
|
@ -721,8 +721,8 @@ static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,
|
|||
|
||||
if (hsfs & HSFS_FCERR) {
|
||||
uint16_t hsfc;
|
||||
addr = readl_(&g_cntlr.ich9_spi->faddr) & 0x01FFFFFF;
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;
|
||||
hsfc = readw_(&cntlr.ich9_spi->hsfc);
|
||||
printk(BIOS_ERR, "Transaction error between offset 0x%08x and "
|
||||
"0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",
|
||||
addr, addr + len - 1, addr, len - 1,
|
||||
|
|
@ -758,17 +758,17 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
|
|||
|
||||
while (offset < end) {
|
||||
/* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
|
||||
|
||||
ich_hwseq_set_addr(offset);
|
||||
|
||||
offset += erase_size;
|
||||
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
hsfc = readw_(&cntlr.ich9_spi->hsfc);
|
||||
hsfc &= ~HSFC_FCYCLE; /* clear operation */
|
||||
hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
|
||||
hsfc |= HSFC_FGO; /* start */
|
||||
writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
|
||||
writew_(hsfc, &cntlr.ich9_spi->hsfc);
|
||||
if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
|
||||
printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
|
||||
ret = -1;
|
||||
|
|
@ -790,7 +790,7 @@ static void ich_read_data(uint8_t *data, int len)
|
|||
|
||||
for (i = 0; i < len; i++) {
|
||||
if ((i % 4) == 0)
|
||||
temp32 = readl_(g_cntlr.data + i);
|
||||
temp32 = readl_(cntlr.data + i);
|
||||
|
||||
data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;
|
||||
}
|
||||
|
|
@ -812,20 +812,20 @@ static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,
|
|||
}
|
||||
|
||||
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
|
||||
|
||||
while (len > 0) {
|
||||
block_len = min(len, g_cntlr.databytes);
|
||||
block_len = min(len, cntlr.databytes);
|
||||
if (block_len > (~addr & 0xff))
|
||||
block_len = (~addr & 0xff) + 1;
|
||||
ich_hwseq_set_addr(addr);
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
hsfc = readw_(&cntlr.ich9_spi->hsfc);
|
||||
hsfc &= ~HSFC_FCYCLE; /* set read operation */
|
||||
hsfc &= ~HSFC_FDBC; /* clear byte count */
|
||||
/* set byte count */
|
||||
hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
|
||||
hsfc |= HSFC_FGO; /* start */
|
||||
writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
|
||||
writew_(hsfc, &cntlr.ich9_spi->hsfc);
|
||||
|
||||
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
|
||||
return 1;
|
||||
|
|
@ -857,11 +857,11 @@ static void ich_fill_data(const uint8_t *data, int len)
|
|||
temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);
|
||||
|
||||
if ((i % 4) == 3) /* 32 bits are full, write them to regs. */
|
||||
writel_(temp32, g_cntlr.data + (i - (i % 4)));
|
||||
writel_(temp32, cntlr.data + (i - (i % 4)));
|
||||
}
|
||||
i--;
|
||||
if ((i % 4) != 3) /* Write remaining data to regs. */
|
||||
writel_(temp32, g_cntlr.data + (i - (i % 4)));
|
||||
writel_(temp32, cntlr.data + (i - (i % 4)));
|
||||
}
|
||||
|
||||
static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
|
||||
|
|
@ -880,24 +880,24 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
|
|||
}
|
||||
|
||||
/* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */
|
||||
writew_(readw_(&g_cntlr.ich9_spi->hsfs), &g_cntlr.ich9_spi->hsfs);
|
||||
writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);
|
||||
|
||||
while (len > 0) {
|
||||
block_len = min(len, g_cntlr.databytes);
|
||||
block_len = min(len, cntlr.databytes);
|
||||
if (block_len > (~addr & 0xff))
|
||||
block_len = (~addr & 0xff) + 1;
|
||||
|
||||
ich_hwseq_set_addr(addr);
|
||||
|
||||
ich_fill_data(buf, block_len);
|
||||
hsfc = readw_(&g_cntlr.ich9_spi->hsfc);
|
||||
hsfc = readw_(&cntlr.ich9_spi->hsfc);
|
||||
hsfc &= ~HSFC_FCYCLE; /* clear operation */
|
||||
hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */
|
||||
hsfc &= ~HSFC_FDBC; /* clear byte count */
|
||||
/* set byte count */
|
||||
hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);
|
||||
hsfc |= HSFC_FGO; /* start */
|
||||
writew_(hsfc, &g_cntlr.ich9_spi->hsfc);
|
||||
writew_(hsfc, &cntlr.ich9_spi->hsfc);
|
||||
|
||||
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
|
||||
printk(BIOS_ERR, "SF: write failure at %x\n",
|
||||
|
|
@ -934,7 +934,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
|
|||
flash->name = "Opaque HW-sequencing";
|
||||
|
||||
ich_hwseq_set_addr(0);
|
||||
switch ((g_cntlr.hsfs >> 3) & 3) {
|
||||
switch ((cntlr.hsfs >> 3) & 3) {
|
||||
case 0:
|
||||
flash->sector_size = 256;
|
||||
break;
|
||||
|
|
@ -949,12 +949,12 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
|
|||
break;
|
||||
}
|
||||
|
||||
flash->size = 1 << (19 + (g_cntlr.flcomp & 7));
|
||||
flash->size = 1 << (19 + (cntlr.flcomp & 7));
|
||||
|
||||
flash->ops = &spi_flash_ops;
|
||||
|
||||
if ((g_cntlr.hsfs & HSFS_FDV) && ((g_cntlr.flmap0 >> 8) & 3))
|
||||
flash->size += 1 << (19 + ((g_cntlr.flcomp >> 3) & 7));
|
||||
if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))
|
||||
flash->size += 1 << (19 + ((cntlr.flcomp >> 3) & 7));
|
||||
printk(BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);
|
||||
|
||||
return 0;
|
||||
|
|
@ -1008,16 +1008,16 @@ static int spi_flash_protect(const struct spi_flash *flash,
|
|||
int fpr;
|
||||
uint32_t *fpr_base;
|
||||
|
||||
fpr_base = g_cntlr.fpr;
|
||||
fpr_base = cntlr.fpr;
|
||||
|
||||
/* Find first empty FPR */
|
||||
for (fpr = 0; fpr < g_cntlr.fpr_max; fpr++) {
|
||||
for (fpr = 0; fpr < cntlr.fpr_max; fpr++) {
|
||||
reg = read32(&fpr_base[fpr]);
|
||||
if (reg == 0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (fpr == g_cntlr.fpr_max) {
|
||||
if (fpr == cntlr.fpr_max) {
|
||||
printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
|
||||
return -1;
|
||||
}
|
||||
|
|
@ -1106,12 +1106,12 @@ void spi_finalize_ops(void)
|
|||
|
||||
spi_opprefix = spi_config->opprefixes[0]
|
||||
| (spi_config->opprefixes[1] << 8);
|
||||
writew_(spi_opprefix, g_cntlr.preop);
|
||||
writew_(spi_opprefix, cntlr.preop);
|
||||
for (i = 0; i < ARRAY_SIZE(spi_config->ops); i++) {
|
||||
optype |= (spi_config->ops[i].type & 3) << (i * 2);
|
||||
writeb_(spi_config->ops[i].op, &g_cntlr.opmenu[i]);
|
||||
writeb_(spi_config->ops[i].op, &cntlr.opmenu[i]);
|
||||
}
|
||||
writew_(optype, g_cntlr.optype);
|
||||
writew_(optype, cntlr.optype);
|
||||
}
|
||||
|
||||
__weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config)
|
||||
|
|
|
|||
Loading…
Reference in New Issue