soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/17063 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Brenton Dong
Martin Roth
parent
0a5971c91b
commit
c9b398191e
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@ -19,7 +19,8 @@
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.section ".module_parameters", "aw", @progbits
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/* stack_top indicates the stack to pull MTRR information from. */
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stack_top:
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.global post_car_stack_top
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post_car_stack_top:
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.long 0
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.long 0
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@ -38,7 +39,7 @@ _start:
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invd
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/* Set up new stack. */
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mov stack_top, %esp
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mov post_car_stack_top, %esp
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/*
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* Honor variable MTRR information pushed on the stack with the
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@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/x86/cache
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cache_as_ram.S
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bootblock-y += bootblock/bootblock.c
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bootblock-y += car.c
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bootblock-y += flash_ctrlr.c
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@ -23,6 +22,12 @@ bootblock-y += spi.c
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bootblock-y += tsc_freq.c
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bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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ifeq ($(CONFIG_FSP_CAR),y)
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bootblock-y += bootblock/cache_as_ram_fsp.S
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else
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bootblock-y += bootblock/cache_as_ram.S
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endif
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romstage-y += car.c
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romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
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romstage-y += flash_ctrlr.c
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@ -79,7 +84,6 @@ ramstage-y += sram.c
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ramstage-y += spi.c
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ramstage-y += xhci.c
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postcar-y += exit_car.S
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postcar-y += flash_ctrlr.c
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postcar-y += memmap.c
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postcar-y += mmap_boot.c
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@ -87,6 +91,12 @@ postcar-y += spi.c
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postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
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postcar-y += tsc_freq.c
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ifeq ($(CONFIG_FSP_CAR),y)
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postcar-y += exit_car_fsp.S
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else
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postcar-y += exit_car.S
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endif
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verstage-y += car.c
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verstage-y += flash_ctrlr.c
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verstage-y += i2c_early.c
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@ -0,0 +1,111 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci_def.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/cr.h>
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#include <cpu/x86/post_code.h>
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#include <soc/cpu.h>
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#include <../../../arch/x86/walkcbfs.S>
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#define FSP_HDR_OFFSET 0x94
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.global bootblock_pre_c_entry
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bootblock_pre_c_entry:
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.global cache_as_ram
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cache_as_ram:
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post_code(0x21)
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/* find fsp in cbfs */
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lea fsp_name, %esi
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mov $1f, %esp
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jmp walkcbfs_asm
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1:
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cmp $0, %eax
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jz .halt_forever
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mov CBFS_FILE_OFFSET(%eax), %ebx
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bswap %ebx
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add %eax, %ebx
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add FSP_HDR_OFFSET, %ebx
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/*
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* ebx = FSP INFO HEADER
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* Calculate entry into FSP
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*/
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mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */
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add 0x1c(%ebx), %eax /* add the FSP ImageBase */
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/*
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* Pass early init variables on a fake stack (no memory yet)
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* as well as the return location
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*/
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lea CAR_init_stack, %esp
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/* call FSP binary to setup temporary stack */
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jmp *%eax
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/*
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* If the TempRamInit API is successful, then when returning, the ECX and
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* EDX registers will point to the temporary but writeable memory range
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* available to the bootloader where ECX is the start and EDX is the end of
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* the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more
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* information.
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*
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* Return Values:
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* EAX | Return Status
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* ECX | Temporary Memory Start
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* EDX | Temporary Memory End
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* EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call
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*/
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CAR_init_done:
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/* Setup bootblock stack */
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mov %edx, %esp
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/* clear CAR_GLOBAL area as it is not shared */
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cld
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xor %eax, %eax
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movl $(_car_global_end), %ecx
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movl $(_car_global_start), %edi
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sub %edi, %ecx
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rep stosl
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/* We can call into C functions now */
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call bootblock_c_entry
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/* Never reached */
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.halt_forever:
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post_code(POST_DEAD_CODE)
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hlt
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jmp .halt_forever
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CAR_init_params:
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.long 0 /* Microcode Location */
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.long 0 /* Microcode Length */
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.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
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.long CONFIG_ROM_SIZE /* Total Firmware Length */
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CAR_init_stack:
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.long CAR_init_done
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.long CAR_init_params
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fsp_name:
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.ascii "blobs/fspt.bin\x00"
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@ -0,0 +1,47 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cr.h>
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#include <soc/cpu.h>
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/*
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* This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
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* This version of chipset_teardown_car sets up the stack, then bypasses
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* the rest of arch/x86/exit_car.S and calls main() itself instead of
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* returning to _start. In main(), the TempRamExit FSP API is called
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* to tear down the CAR and set up caching which can be overwritten
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* after the API call. More info can be found in the Apollo Lake FSP
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* Integration Guide included with the FSP binary. The below
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* caching settings are based on an 8MiB Flash Size given as a
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* parameter to TempRamInit.
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*
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* TempRamExit MTRR Settings:
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* 0x00000000 - 0x0009FFFF | Write Back
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* 0x000C0000 - Top of Low Memory | Write Back
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* 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect
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* 0x100000000 - Top of High Memory | Write Back
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*/
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.text
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.global chipset_teardown_car
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chipset_teardown_car:
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/* Set up new stack. */
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mov post_car_stack_top, %esp
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/* Call C code */
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call main
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