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soc/amd/mendocino: Mark PCIe GPP bridges as hidden instead of off 

When one of the General-Purpose PCIe bridges is not used, it doesn't
show up on the PCI bus at all, so coreboot notes it as an issue in the
devicetree. This happens even if the device is marked as off.
To solve this, we're marking the GPP bridge devices in devicetree as
hidden, so they'll only show up in devicetree if they're actually used
on a mainboard.

BUG=None
TEST=Don't see the "PCI: Leftover static devices:" warning for these in
the boot console.
BRANCH=skyrim

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I517776e4dedc70e957a0c836ab3c2e5d49e156d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74526
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Martin Roth 2023-04-19 13:37:40 -06:00 committed by Felix Held
parent 0cca0176d5
commit c9ce5f6ec8
2 changed files with 10 additions and 10 deletions
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8
src/soc/amd/mendocino/chipset_mendocino.cb
View File

@ -10,10 +10,10 @@ chip soc/amd/mendocino
device pci 01.0 on end # Dummy Host Bridge
device pci 02.0 on end # Dummy Host Bridge, do not disable
device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A

12
src/soc/amd/mendocino/chipset_rembrandt.cb
View File

@ -10,12 +10,12 @@ chip soc/amd/mendocino
device pci 01.0 on end # Dummy Host Bridge
device pci 02.0 on end # Dummy Host Bridge, do not disable
device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_1 off ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 off ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 off ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_4 off ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_5 off ops amd_external_pcie_gpp_ops end
device pci 02.1 alias gpp_bridge_0 hidden ops amd_external_pcie_gpp_ops end
device pci 02.2 alias gpp_bridge_1 hidden ops amd_external_pcie_gpp_ops end
device pci 02.3 alias gpp_bridge_2 hidden ops amd_external_pcie_gpp_ops end
device pci 02.4 alias gpp_bridge_3 hidden ops amd_external_pcie_gpp_ops end
device pci 02.5 alias gpp_bridge_4 hidden ops amd_external_pcie_gpp_ops end
device pci 02.6 alias gpp_bridge_5 hidden ops amd_external_pcie_gpp_ops end
device pci 08.0 on end # Dummy Host Bridge, do not disable
device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A