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soc/intel/jasperlake: Clean up iomap.h and systemagent.h 

List of changes:
1. Convert inconsistent white space into tab.
2. Group together all MCHBAR offset macros.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ief13406b0116ce0f0b7472e5b133b3fac06f6e27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This commit is contained in:
Subrata Banik 2020-09-13 17:26:26 +05:30 committed by Michael Niewöhner
parent 8ca0b21060
commit c9d598a581
2 changed files with 19 additions and 20 deletions
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2
src/soc/intel/jasperlake/include/soc/iomap.h
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@ -47,7 +47,7 @@
#define GFXVT_BASE_ADDRESS 0xfed90000 #define GFXVT_BASE_ADDRESS 0xfed90000
#define GFXVT_BASE_SIZE 0x1000 #define GFXVT_BASE_SIZE 0x1000
#define IPUVT_BASE_ADDRESS 0xfed92000 #define IPUVT_BASE_ADDRESS 0xfed92000
#define IPUVT_BASE_SIZE 0x1000 #define IPUVT_BASE_SIZE 0x1000
#define VTVC0_BASE_ADDRESS 0xfed91000 #define VTVC0_BASE_ADDRESS 0xfed91000

37
src/soc/intel/jasperlake/include/soc/systemagent.h
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@ -9,40 +9,39 @@
#define EPBAR 0x40 #define EPBAR 0x40
#define DMIBAR 0x68 #define DMIBAR 0x68
#define CAPID0_A 0xe4 #define CAPID0_A 0xe4
#define VTD_DISABLE (1 << 23) #define VTD_DISABLE (1 << 23)
#define BIOS_RESET_CPL 0x5da8
#define GFXVTBAR 0x5400 #define GFXVTBAR 0x5400
#define EDRAMBAR 0x5408 #define EDRAMBAR 0x5408
#define VTVC0BAR 0x5410 #define VTVC0BAR 0x5410
#define REGBAR 0x5420 #define REGBAR 0x5420
#define MCH_DDR_POWER_LIMIT_LO 0x58e0
#define MCH_DDR_POWER_LIMIT_HI 0x58e4
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
#define BIOS_RESET_CPL 0x5da8
#define IMRBASE 0x6a40
#define IMRLIMIT 0x6a48
#define IPUVTBAR 0x7880 #define IPUVTBAR 0x7880
#define TBT0BAR 0x7888 #define TBT0BAR 0x7888
#define TBT1BAR 0x7890 #define TBT1BAR 0x7890
#define TBT2BAR 0x7898 #define TBT2BAR 0x7898
#define TBT3BAR 0x78A0 #define TBT3BAR 0x78a0
#define MAX_TBT_PCIE_PORT 4 #define MAX_TBT_PCIE_PORT 4
#define VTBAR_ENABLED 0x01 #define VTBAR_ENABLED 0x01
#define VTBAR_MASK 0x7ffffff000ull #define VTBAR_MASK 0x7ffffff000ull
#define MCH_PKG_POWER_LIMIT_LO 0x59a0
#define MCH_PKG_POWER_LIMIT_HI 0x59a4
#define MCH_DDR_POWER_LIMIT_LO 0x58e0
#define MCH_DDR_POWER_LIMIT_HI 0x58e4
#define IMRBASE 0x6A40
#define IMRLIMIT 0x6A48
static const struct sa_mmio_descriptor soc_vtd_resources[] = { static const struct sa_mmio_descriptor soc_vtd_resources[] = {
{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" }, { GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
{ IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" }, { IPUVTBAR, IPUVT_BASE_ADDRESS, IPUVT_BASE_SIZE, "IPUVTBAR" },
{ TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" }, { TBT0BAR, TBT0_BASE_ADDRESS, TBT0_BASE_SIZE, "TBT0BAR" },
{ TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" }, { TBT1BAR, TBT1_BASE_ADDRESS, TBT1_BASE_SIZE, "TBT1BAR" },
{ TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" }, { TBT2BAR, TBT2_BASE_ADDRESS, TBT2_BASE_SIZE, "TBT2BAR" },
{ TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" }, { TBT3BAR, TBT3_BASE_ADDRESS, TBT3_BASE_SIZE, "TBT3BAR" },
{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" }, { VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
}; };
#define V_P2SB_CFG_IBDF_BUS 0 #define V_P2SB_CFG_IBDF_BUS 0