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Add bifferboard 

This commit adds support for Bifferboard, a 32MB 486 PC

Change-Id: Iad790ebf242ef07bf6298f8e3577783e5e743113
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/810
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Rudolf Marek 2012-03-25 19:55:43 +02:00 committed by Stefan Reinauer
parent ae012486e8
commit c9da0157c7
8 changed files with 180 additions and 0 deletions
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3
src/mainboard/Kconfig
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@ -36,6 +36,8 @@ config VENDOR_AZZA
bool "AZZA"
config VENDOR_BCOM
bool "BCOM"
config VENDOR_BIFFEROS
bool "Bifferos"
config VENDOR_BIOSTAR
bool "Biostar"
config VENDOR_BROADCOM
@ -143,6 +145,7 @@ source "src/mainboard/avalue/Kconfig"
source "src/mainboard/axus/Kconfig"
source "src/mainboard/azza/Kconfig"
source "src/mainboard/bcom/Kconfig"
source "src/mainboard/bifferos/Kconfig"
source "src/mainboard/biostar/Kconfig"
source "src/mainboard/broadcom/Kconfig"
source "src/mainboard/compaq/Kconfig"

36
src/mainboard/bifferos/Kconfig Normal file
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@ -0,0 +1,36 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if VENDOR_BIFFEROS
choice
prompt "Mainboard model"
config BOARD_BIFFEROS_BIFFERBOARD
bool "Bifferboard"
endchoice
source "src/mainboard/bifferos/bifferboard/Kconfig"
config MAINBOARD_VENDOR
string
default "Bifferos"
endif # VENDOR_BIFFEROS

19
src/mainboard/bifferos/bifferboard/Kconfig Normal file
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@ -0,0 +1,19 @@
if BOARD_BIFFEROS_BIFFERBOARD
config BOARD_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select ROMCC
select BOARD_ROMSIZE_KB_128
select NORTHBRIDGE_RDC_R8610
select SOUTHBRIDGE_RDC_R8610
config MAINBOARD_DIR
string
default bifferos/bifferboard
config MAINBOARD_PART_NUMBER
string
default "Bifferos"
endif # BOARD_BIFFEROS_BIFFERBOARD

1
src/mainboard/bifferos/bifferboard/Makefile.inc Normal file
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@ -0,0 +1 @@
ROMCCFLAGS := -mcpu=i386 -O

23
src/mainboard/bifferos/bifferboard/chip.h Normal file
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@ -0,0 +1,23 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
extern struct chip_operations mainboard_ops;
struct mainboard_config {};

8
src/mainboard/bifferos/bifferboard/devicetree.cb Normal file
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@ -0,0 +1,8 @@
chip northbridge/rdc/r8610
device pci_domain 0 on
device pci 0.0 on end
chip southbridge/rdc/r8610 # Southbridge
device pci 7.0 on end # SB
end
end
end

26
src/mainboard/bifferos/bifferboard/mainboard.c Normal file
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@ -0,0 +1,26 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <device/device.h>
#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Bifferos Bifferboard")
};

64
src/mainboard/bifferos/bifferboard/romstage.c Normal file
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@ -0,0 +1,64 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <arch/hlt.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
static void main(void)
{
uint32_t tmp;
post_code(0x05);
/* Set timer1 to pulse generator 15us for memory refresh */
outb(0x54, 0x43);
outb(0x12, 0x41);
/* CPU setup, romcc pukes on invd() */
asm volatile ("invd");
enable_cache();
/* Set serial base */
pci_write_config32(PCI_DEV(0,7,0), 0x54, 0x3f8);
/* serial IRQ disable, LPC disable, COM2 goes to LPC, internal UART for COM1 */
pci_write_config32(PCI_DEV(0,7,0), 0x50, 0x84101012);
console_init();
/* memory init */
pci_write_config32(PCI_DEV(0,0,0), 0x68, 0x6c99f);
pci_write_config32(PCI_DEV(0,0,0), 0x6c, 0x800451);
pci_write_config32(PCI_DEV(0,0,0), 0x70, 0x4000003);
/* memory phase/buffer strength for read and writes */
tmp = pci_read_config32(PCI_DEV(0,0,0), 0x64);
tmp &= 0x0FF00FFFF;
tmp |= 0x790000;
pci_write_config32(PCI_DEV(0,0,0), 0x64, tmp);
/* Route Cseg, Dseg, Eseg and Fseg to RAM */
pci_write_config32(PCI_DEV(0,0,0), 0x84, 0x3ffffff0);
}