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nb/intel/gm45/acpi/gm45.asl: Drop dead code 

This code is not even being build-tested. Drop it before it grows moss.

Change-Id: I41a4f73df7fdd372ec7a80a41c8216c502054c39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43262
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-08 00:46:01 +02:00
parent b9bdcaecc1
commit c9e42b98ef
1 changed files with 0 additions and 28 deletions
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28
src/northbridge/intel/gm45/acpi/gm45.asl
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@ -12,16 +12,6 @@ Device (PDRC)
// This does not seem to work correctly yet - set values statically for
// now.
//Name (PDRS, ResourceTemplate() {
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
// Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
// Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
// Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
//})
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)
Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000)
@ -36,24 +26,6 @@ Device (PDRC)
// Current Resource Settings
Method (_CRS, 0, Serialized)
{
//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
Return(PDRS)
}
}