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Clean up AMD romstage.c whitespace indent issues 

Change-Id: I1713f1a3b548cb8e8ea5cf57eef95486ceb05ab9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/538
Tested-by: build bot (Jenkins)
Reviewed-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Marc Jones 2012-01-17 15:41:03 -07:00 committed by Stefan Reinauer
parent db89ec975c
commit c9ea327a45
3 changed files with 183 additions and 179 deletions
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45
src/mainboard/amd/inagua/romstage.c
View File

@ -38,13 +38,13 @@
#include <arch/cpu.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
u32 agesawrapper_amdinitmmio (void);
u32 agesawrapper_amdinitreset (void);
u32 agesawrapper_amdinitearly (void);
u32 agesawrapper_amdinitenv (void);
u32 agesawrapper_amdinitlate (void);
u32 agesawrapper_amdinitpost (void);
u32 agesawrapper_amdinitmid (void);
u32 agesawrapper_amdinitmmio(void);
u32 agesawrapper_amdinitreset(void);
u32 agesawrapper_amdinitearly(void);
u32 agesawrapper_amdinitenv(void);
u32 agesawrapper_amdinitlate(void);
u32 agesawrapper_amdinitpost(void);
u32 agesawrapper_amdinitmid(void);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
@ -73,45 +73,48 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x37);
val = agesawrapper_amdinitreset();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
val);
}
post_code(0x38);
printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
post_code(0x39);
val = agesawrapper_amdinitearly ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
val = agesawrapper_amdinitearly();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
post_code(0x40);
val = agesawrapper_amdinitpost ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
val = agesawrapper_amdinitpost();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
post_code(0x41);
val = agesawrapper_amdinitenv ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
val = agesawrapper_amdinitenv();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
/* Initialize i8259 pic */
post_code(0x41);
setup_i8259 ();
setup_i8259();
/* Initialize i8254 timers */
post_code(0x42);
setup_i8254 ();
setup_i8254();
post_code(0x50);
copy_and_run(0);
post_code(0x54); // Should never see this post code.
}

26
src/mainboard/amd/torpedo/get_bus_conf.c
View File

@ -27,7 +27,6 @@
#include "SbEarly.h"
#include "agesawrapper.h"
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
@ -59,9 +58,6 @@ u32 sbdn_sb900;
static u32 get_bus_conf_done = 0;
void get_bus_conf(void)
{
u32 status;
@ -74,7 +70,8 @@ void get_bus_conf(void)
get_bus_conf_done = 1;
printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
printk(BIOS_DEBUG,
"Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n");
/*
* This is the call to AmdInitLate. It is really in the wrong place, conceptually,
* but functionally within the coreboot model, this is the best place to make the
@ -91,8 +88,9 @@ void get_bus_conf(void)
* becomes the best place for this call.
*/
status = agesawrapper_amdinitlate();
if(status) {
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n", status);
if (status) {
printk(BIOS_DEBUG, "agesawrapper_amdinitlate failed: %x \n",
status);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitlate\n");
@ -106,7 +104,6 @@ void get_bus_conf(void)
bus_type[i] = 0; /* default ISA bus. */
}
bus_type[0] = 1; /* pci */
// bus_sb900[0] = (sysconf.pci1234[0] >> 16) & 0xff;
@ -115,8 +112,6 @@ void get_bus_conf(void)
/* sb900 */
dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4));
if (dev) {
bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
@ -127,9 +122,12 @@ void get_bus_conf(void)
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, i));
dev =
dev_find_slot(bus_sb900[0],
PCI_DEVFN(sbdn_sb900 + 0x14, i));
if (dev) {
bus_sb900[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_sb900[2 + i] =
pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
@ -137,10 +135,10 @@ void get_bus_conf(void)
for (j = bus_sb900[2]; j < bus_isa; j++)
bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
sb_Late_Post();
printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
printk(BIOS_DEBUG,
"Mainboard - Get_bus_conf.c - get_bus_conf - End.\n");
}

39
src/mainboard/amd/torpedo/romstage.c
View File

@ -40,15 +40,15 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
u32 val;
post_code(0x35);
val = agesawrapper_amdinitmmio();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n", val);
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitmmio failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitmmio\n");
@ -78,44 +78,48 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x36);
val = agesawrapper_amdinitreset();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n", val);
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitreset failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n");
post_code(0x37);
val = agesawrapper_amdinitearly ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n", val);
val = agesawrapper_amdinitearly();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitearly failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitearly\n");
post_code(0x38);
val = agesawrapper_amdinitpost ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n", val);
val = agesawrapper_amdinitpost();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitpost failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitpost\n");
post_code(0x39);
sb_before_pci_init ();
sb_before_pci_init();
printk(BIOS_DEBUG, "Got past sb_before_pci_init\n");
post_code(0x40);
val = agesawrapper_amdinitenv ();
if(val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n", val);
val = agesawrapper_amdinitenv();
if (val) {
printk(BIOS_DEBUG, "agesawrapper_amdinitenv failed: %x \n",
val);
}
printk(BIOS_DEBUG, "Got past agesawrapper_amdinitenv\n");
/* Initialize i8259 pic */
post_code(0x41);
setup_i8259 ();
setup_i8259();
printk(BIOS_DEBUG, "Got past setup_i8259\n");
/* Initialize i8254 timers */
post_code(0x42);
setup_i8254 ();
setup_i8254();
printk(BIOS_DEBUG, "Got past setup_i8254\n");
post_code(0x43);
@ -124,4 +128,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x44); // Should never see this post code.
}