bd82x6x: Add config option to force SATA link to different speeds.

Certain SATA devices claim to support SATA 6 Gbps, but in fact have
bugs. For these devices, add a config option to force the SATA link
speed to something other than default.

Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb
Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
Reviewed-on: http://review.coreboot.org/2765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Shawn Nematbakhsh 2013-03-14 10:44:13 -07:00 committed by Ronald G. Minnich
parent 645b376ec8
commit c9fc0297ad
2 changed files with 18 additions and 0 deletions

View File

@ -70,6 +70,17 @@ struct southbridge_intel_bd82x6x_config {
uint32_t sata_port0_gen3_tx; uint32_t sata_port0_gen3_tx;
uint32_t sata_port1_gen3_tx; uint32_t sata_port1_gen3_tx;
/**
* SATA Interface Speed Support Configuration
*
* Only the lower two bits have a meaning:
* 00 - No effect (leave as chip default)
* 01 - 1.5 Gb/s maximum speed
* 10 - 3.0 Gb/s maximum speed
* 11 - 6.0 Gb/s maximum speed
*/
uint8_t sata_interface_speed_support;
uint32_t gen1_dec; uint32_t gen1_dec;
uint32_t gen2_dec; uint32_t gen2_dec;
uint32_t gen3_dec; uint32_t gen3_dec;

View File

@ -135,6 +135,13 @@ static void sata_init(struct device *dev)
reg32 = read32(abar + 0x00); reg32 = read32(abar + 0x00);
reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS reg32 |= 0x0c006000; // set PSC+SSC+SALP+SSS
reg32 &= ~0x00020060; // clear SXS+EMS+PMS reg32 &= ~0x00020060; // clear SXS+EMS+PMS
/* Set ISS, if available */
if (config->sata_interface_speed_support)
{
reg32 &= ~0x00f00000;
reg32 |= (config->sata_interface_speed_support & 0x03)
<< 20;
}
write32(abar + 0x00, reg32); write32(abar + 0x00, reg32);
/* PI (Ports implemented) */ /* PI (Ports implemented) */
write32(abar + 0x0c, config->sata_port_map); write32(abar + 0x0c, config->sata_port_map);