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xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices 

The values can be used during SMBIOS type 16 creation.

Tested=On OCP Delta Lake, dmidecode -t 16 to verify.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
        Location: System Board Or Motherboard
        Use: System Memory
        Error Correction Type: Single-bit ECC
        Maximum Capacity: 1146 GB
        Error Information Handle: Not Provided
        Number Of Devices: 6

Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Johnny Lin 2021-01-25 15:00:48 +08:00 committed by Patrick Georgi
parent d92d7cb515
commit ca083db4d3
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/xeon_sp/cpx/romstage.c
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@ -60,6 +60,9 @@ void save_dimm_info(void)
return;
}
memset(mem_info, 0, sizeof(*mem_info));
/* According to Dear Customer Letter it's 1.12 TB per processor. */
mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET;
mem_info->number_of_devices = CONFIG_DIMM_MAX;
dimm_max = ARRAY_SIZE(mem_info->dimm);
vdd_voltage = get_ddr_voltage(hob->DdrVoltage);
/* For now only implement for one socket and hard-coded for DDR4 */